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ESD testing : from components to systems--Overview and Article Index



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Article Index:

  1. Introduction


  2. Human Body Model (HBM)


  3. Machine Model (MM)


  4. Charged Device Model (CDM)


  5. Transmission Line Pulse (TLP) Testing


  6. Very Fast Transmission Line Pulse (VF-TLP) Testing


  7. IEC 61000-4-2


  8. Human Metal Model (HMM)


  9. IEC 61000-4-5


  10. Cable Discharge Event (CDE)


  11. Latchup


  12. Electrical Overstress (EOS)


  13. Electromagnetic Compatibility (EMC)

Above: ESD SIMULATOR tool.

Overview

This guide -- ESD Testing: From Components to Systems -- was targeted for the semiconductor process and device engineer, the circuit designer, the ESD/latchup test engineer, and the ESD engineer. In this guide, a balance is established between the technology and testing.

The first goal of this guide is to teach the ESD models used today. There are many ESD test models, and more types are being developed today and in the future.

The second goal is to show recent test systems and test standards. Significant change in both the test methodologies and issues are leading to proposal of new ESD models, introduction of new standards, and an impact on product diversity and product variety.

The third goal is to expose the reader to the growing number of new testing methodologies, concepts, and equipment. In this guide, commercial test equipment is shown as an example to demonstrate the "state-of-the-art" of ESD testing. Significant progress has been made in recent years in ESD, EOS, and EMC.

The fourth goal, as previously done in the ESD guide series, is to teach testing as an ESD design practice. ESD testing can be used as a design methodology or an ESD tool. ESD testing can lead to understanding of the fundamental practices of ESD design and the ESD design discipline. This practice uses ESD testing for "de-bugging" and diagnosis.

The fifth goal is to provide a guide that can view the different test methods independently.

Each section is independent so that the reader can study or read about a test model independent of the other test models.

The sixth goal is to provide a text where one can compare the interrelationship between one ESD model and another ESD model. In many cases, there is commonality between the test waveform, the test procedure, and even failure mechanisms.

The seventh goal is to provide a text structure similar to a standard or standard test method, but read easier than reading a standard document. The goal was also to reduce the level of details of the standard to simplify the understanding.

The guide ESD Testing: From Components to Systems consists of the following:

Section 1 introduces the reader to fundamentals and concepts of the electrostatic discharge (ESD) models and issues.

Section 2 discusses the human body model (HBM). It discusses the purpose, scope, waveforms, test procedures, and test systems. In this section, both the wafer-level and product-level test methodologies are discussed. This section includes HBM failure mechanisms to circuit solutions. Alternative test methodologies such as sampling and split fixture methods are reviewed.

Section 3 discusses the machine model (MM). It discusses the purpose, scope, waveforms, test procedures, and test systems. In this section, both the wafer-level and product-level test methodologies are discussed. This section includes MM failure mechanisms to circuit solutions. Alternative test methodologies such as the small charge model (SCM) are discussed.

In addition, correlation relations of HBM to MM ratio are analyzed and reviewed.

Section 4 discusses the charged device model (CDM). It discusses the purpose, scope, wave forms, CDM test procedures, and CDM test systems. This section includes CDM failure mechanisms to circuit solutions to avoid CDM failures. Alternative test methodologies such as the socketed device model (SDM) and charged board model (CBM) are discussed.

Section 5 discusses the transmission line pulse (TLP) methodology and its importance in the semiconductor industry and ESD development. It discusses the purpose, scope, waveforms, TLP pulsed I-V characteristics, TLP test procedures, and TLP test system configurations.

TLP current source, time domain reflection (TDR), time domain transmission (TDT), and time domain reflection and transmission (TDRT) configurations is explained Section 6 discusses the very fast transmission line pulse (VF-TLP) methodology. It discusses the purpose, scope, waveforms, VF-TLP pulsed I-V characteristics, VF-TLP test procedures, and VF-TLP test system configurations. Alternative test methods such as ultra fast transmission line pulse (UF-TLP) are discussed.

Section 7 discusses the system-level method, known as IEC 61000-4-2. It discusses the purpose, scope, IEC 61000-4-2 waveforms, IEC 61000-4-2 table configurations, and requirements. Failure mechanisms and circuit solutions to avoid failures are explained.

Section 8 discusses the human metal model (HMM) method. The HMM model has many similarities to the system-level method, known as IEC 61000-4-2. It discusses the purpose, scope, waveforms, HMM table configurations, and requirements as well as the distinctions and commonality to the IEC 61000-4-2 test method.

Section 9 discusses the system-level transient surge method, known as IEC 61000-4-5. It discusses the purpose, scope, IEC 61000-4-5 waveforms, IEC 61000-4-5 table configurations, and requirements. Failure mechanisms and circuit solutions to avoid failures are explained.

The distinction from the IEC 61000-4-2 is highlighted.

Section 10 discusses the cable discharge event (CDE) method. It discusses the purpose, scope, waveforms, cable configurations, and impact on the pulse event. Examples of cable-induced failures are given, as well as circuit- and system-level solutions to avoid chip and system failures.

Section 11 discusses latchup. It addresses latchup testing, characterization, and design. It also addresses latchup test techniques for product-level testing. Technology benchmarking to ground rule development is also briefly discussed.

Section 12 discusses electrical overstress (EOS). It focuses on electrical and thermal safe operating area (SOA) and how EOS occurs. It also focuses on how to distinguish latchup from EOS events.

Section 13 discusses electromagnetic compatibility (EMC). It addresses ESD and EMC testing and characterization methods. It also serves as a brief introduction to this large subject matter.

Hopefully, the guide covers the trends and directions of ESD testing discipline.

Enjoy the text, and enjoy the subject of ESD testing.

Links:

teseq.com

compliance-club.com


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Updated: Saturday, 2017-04-08 11:35 PST