Guide to Reliability of Electrical/Electronic Equipment and Products--Electrostatic Discharge and Electromagnetic Compatibility (part 1)

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1. ELECTROSTATIC DISCHARGE

1.1 What Is Electrostatic Discharge and How Does It Occur?

Electrostatic discharge (ESD), a major cause of failure in electronic components, affects the reliability of electronic systems, including the functioning of an electronic component at any stage-during device fabrication, testing, handling, and assembly; printed circuit board (PCB) assembly and test; system integration and test; and field operation and handling of printed wiring assemblies (PWAs) in the field.

Electrostatic discharge is a charge-driven mechanism because the event occurs as a result of a charge imbalance. The current induced by an ESD event balances the charge between two objects. The ESD event has four major stages:

(1) charge generation, (2) charge transfer, (3) charge conduction, and (4) charge induced damage.

Electrostatic discharge occurs from an accumulation of charges on a surface due to reasons such as contact or friction. The process, called triboelectric charging, can occur when one wearing footwear walks onto a carpeted surface, when an integrated circuit slides through a plastic tray or tube, or during handling of components by handlers or robotic machinery.

In triboelectric charging, there is a transfer of electrons from one surface to the other in which one surface gets negatively charged, due to excess of electrons, and the other gets positively charged, due to a deficiency of electrons in equal measure. Materials differ in their capacity to accumulate or give up electrons.

The increasing miniaturization in electronics and the consequent use of small-geometry devices with thin layers has increased susceptibility to ESD dam age; ESD is a silent killer of electronic devices that can destroy a device in nanoseconds, even at low voltages. Electrostatic discharge causes damage to an electronic device by causing either an excessive voltage stress or an abnormally high current discharge, resulting in catastrophic failure or performance degradation (i.e., a latent defect in the device that may surface later during system operation and cause device failure).

Taking a few simple precautions during device design, assembly, testing, storage, and handling, and the use of good circuit design and PWA layout techniques can minimize the effects of ESD and prevent damage to sensitive electronic components.

Damage is expensive-in the cost of the part; the processes; detection and repair; and in loss of reputation, as well as lost production time. Walking wounded parts can be extremely expensive and although the exact figures are difficult to establish, real overall costs to industry worldwide are certainly measured in terms of many millions, whatever the currency. Once damage has been done, it cannot normally be undone. Therefore, precautions need to be taken from cradle to grave.

1.2 Electrostatic Discharge-Induced Failure Mechanisms

The currents induced by ESD are extremely high. It is the current, directly or indirectly, that causes the physical damage observed in an ESD failure. Direct damage is caused by the power generated during the event. It melts a section of the device causing failure. Indirectly, the current generates a voltage by the ohmic resistance and nonlinear conduction along its path. Small voltages are generated when junctions are operated in a forward bias mode, but large voltages are generated when they are in a reverse bias mode. The reverse bias conduction causes thermal damage at lower current levels because the power dissipation is higher from the higher voltage across the junction. In addition, the voltage generated by this event weakens dielectrics by charge injection. The limiting case for this charge injection is dielectric rupture. Electrostatic discharge can affect an integrated circuit in many ways by causing Thermal overstress leading to melting of the metallization and damage to the various transistor junctions in the device.

Intense electric fields that cause a breakdown of transistor thin gate oxide and the junctions themselves.

Latch-up in the internal circuit of complementary metal oxide semiconductor (CMOS) devices due to parasitic p-n-p-n structures and consequent device failure by electrical and thermal overstresses.

Latent defects caused by ESD may cause the device to malfunction or fail under field conditions. Among the commonly used devices, CMOS ICs are especially susceptible to damage due to ESD.

1.3 Preventing Electrostatic Discharge Damage

Preventing ESD-induced damage in electronic systems requires a multipronged approach that includes application of better design techniques at board and circuit level and observing appropriate precautions during handling of components, testing, assembly, system integration, shipment, and field operation. Protection from ESD looks first to minimize the charge generation and slow the charge transfer by controlling the environment where parts are handled and stored.

Some of the techniques that can be used to reduce ESD-related failures of electronic devices include Use of good circuit design techniques-both by proper choice of components and by using circuit level techniques such as protection networks at critical points in the circuit Use of good grounding and layout techniques. Any charge generated should be discharged to ground in a controlled manner Careful handling of ESD-sensitive components during assembly, production, and testing operations

Use of an ESD-controlled production environment Use of appropriate antistatic packaging Proper shielding of the circuit

All IC manufacturers incorporate various protection circuits on the I/O pins of their ICs. The effectiveness of these protection circuits varies from supplier to supplier and from device type to device type. The fundamental approach in preventing ESD-induced failures is to start by selecting an IC with the appropriate ESD rating. Use a device with a higher ESD immunity that meets the application requirement to reduce the incidence of failures due to ESD. Electromagnetic interference (EMI) and ESD are closely related and can be controlled by using similar methods (ESD can be treated as a subset of EMI). Following are brief descriptions of techniques used to reduce the effects of ESD on electronic systems.

Circuit Design Techniques

High-speed logic transitions cause radiation of high-frequency fields resulting in interference to other devices on the PWA and to sensitive circuits in close proximity. Avoid high-speed devices in the design unless they are needed. But, for today's designs to be competitive requires the use of high speed ICs.

Anticipate problems that could arise in the field and tailor your circuit design appropriately.

Although IC manufacturers provide protective networks consisting of di odes to protect a CMOS device against ESD damage, a higher level of protection using external components is recommended in vulnerable circuit designs.

Use transient suppressor diodes at critical points in the circuit because they respond fast and clamp the voltage to a safe value when an overvoltage transient occurs. Keep the transient suppressor very close to the device terminals. Long leads and long PCB traces have parasitic inductances that cause voltage overshoots and ringing problems (if there is an ESD pulse).

A typical method for suppressing ESD transients, which can be used at the input stage of a circuit, is to slip a ferrite bead on the input lead to the ground.

Use series resistors to limit the rate of discharge.

A good low-impedance ground can divert the energy of the ESD transient efficiently. Maintaining a clean ground holds the key to the proper functioning of many electronic circuits using a mixture of analog and digital circuits.

Proper Printed Circuit Board Design

A properly routed PCB significantly contributes to ESD reduction. Magnetic flux lines exist in all energized cards due to the presence of various components and current flow through the circuit. A large loop area formed by conducting paths will enclose more of the magnetic flux, inducing current in the loop (due to the loop acting as an antenna). This loop current causes interfering fields which affect components in the circuit and the functioning of the circuit (closely routing supply and ground lines reduces loop areas).

Provide a large ground area on a PCB; convert unused area into a ground plane.

Place sensitive electronic components away from potential sources of ESD (such as transformers, coils, and connectors).

Run ground lines between very long stretches of signal lines to reduce loop areas.

Keep sensitive electronic components away from board edges so that human operators cannot accidentally cause ESD damage while handling the boards.

Multilayer boards with separate ground planes are preferred to double-sided boards.

Avoid edge-triggered devices. Instead use level-sensing logic with a validation strobe to improve ESD immunity of the circuit.

360° contact with the shield is necessary to prevent antenna effects (i.e., radiated fields).

Packaging guidelines, as applicable to EMI reduction, should be followed to reduce susceptibility to outside fields and to prevent unwanted radiation that can affect nearby equipment.

At the system level, include a marked wrist strap stud where possible.

Proper Materials for Packaging and Handling

Insulating materials have a surface resistivity greater than 10^14 Ohm/square and retain charge. It is advisable to keep insulating materials such as polyethylene, ceramics, and rubber away from electronic components and assembly areas.

Antistatic materials have a surface resistivity of 10^9 and 10^14 Ohm/square and resist the generation of static electricity. These materials have a short life for reuse and are meant for limited reuse applications, such as storing PWAs and electronic components. In view of the high surface resistivity, connecting this material to ground will not be effective in bleeding off any accumulated charge.

Static dissipative materials have a surface resistivity of 10^5 and 10^9 Ohm/square.

Due to the low surface resistivity, charges on a component can be diverted to ground if the material is used to protect a component against static charge and the static dissipative shield is grounded. Static charges can be generated in such materials by friction, but due to better surface conductivity the charges will spread across the surface. Generally such materials are used to cover floors, tabletops, assembly areas, and aprons.

The surface resistivity of conductive materials is less than 10^5 Ohm/square.

The charge accumulated on the surface of conductive material can be easily discharged to ground. Materials used for packaging electronic components and PWAs are generally plastics with conductive material impregnated.

Assembly and Production Techniques

No item should be allowed inside the ESD protect work area (EPA) that can generate and hold electrostatic charge. Examples include Packaging of polystyrene, untreated cling- and shrink-film, etc., whether for sensitive or non-sensitive parts (this charged packaging can come into contact with sensitive parts) Polystyrene or similar cups or other containers Photocopiers

Sensitive parts should be packaged in low-charging, static-shielding containers (such as bags) when taken out of an EPA.

Sensitive parts should be kept well away from strong electrostatic fields (e.g., CRT monitors) Very strong electrostatic field generators, such as contactors, arc welders and so on, should be kept well away from the EPA.

Any sensitive part brought into the EPA should be resistively grounded or otherwise discharged before use. This can be through contact with a wrist-strapped person, through a resistively grounded (nonmetallic) bench, through ionization, or by other suitable means.

Avoid potential differences between device pins during handling.

CMOS ICs should be stored in antistatic tubes, bins, or conductive foams specially designed for storage. The conductive surfaces in contact with the CMOS devices will bleed off the accumulated charges.

For soldering CMOS devices in PCBs, use a soldering iron in which the tip has a proper ground connection. Tools used to insert or remove CMOS ICs from boards or sockets should also be properly grounded.

Do not insert or remove devices when the circuit power is on to prevent damage due to transient voltages.

Unused communication connectors should be covered with static dissipative material when not in use to prevent charge buildup.

Everyone in an EPA should be resistively grounded. In many cased, the most effective method is by the use of a wrist strap, but for mobile operators where the floor has a good defined resistance to ground, footstraps or conductive footwear may be used except while seated.

Many garments can be static generating. Electrostatic discharge-protective garments should be worn to cover any static-generating clothes in the EPA. These garments need a path to ground, which typically will be through the skin and the wrist strap.

Working surfaces need to be resistively grounded, typically through 1 M-ohm, and to have a surface-to-surface resistance of less than 1000 M-ohm. In few cases, metal surfaces may be used, but in general a point-to-point resistance of greater than 750 K-ohm should be used.

Where grounding through resistance is inappropriate, air ionizers should be considered as a means of preventing static buildup.

Slightly higher humidity conditions provide a means to discharge any charge accumulated to ground and provide protection against static electricity buildup.

Do not use tools with plastic handles (due to the triboelectric effect).

Printed wire assemblies should be stored in antistatic bags.

Antistatic precautions should be observed while handling PWAs in the field.

Electrostatic discharge awareness programs should be conducted periodically.


FIGURE 1 Factors that impact the level of electrostatic discharge to ICs on PWAs.

1.4 The Electrostatic Discharge Threat at the Printed Wire Assembly Level

Much effort has been put into characterizing the impact of electrostatic discharge on individual integrated circuits and on completed equipment such as computers.

However, less time has been spent characterizing the ESD threat to ICs mounted on printed circuit boards. Since completed equipment can only be manufactured by mounting the ICs on subassemblies, the ESD threat to PCB-mounted ICs is an important concern.

Computer simulations have shown that the ESD threat to ICs mounted on PCBs may significantly exceed the threat to unmounted, individual ICs. Factors that impact ESD at the PWA are shown graphically in Figure 1 and are discussed in the following sections.

Sources of Electrostatic Discharge

While ESD threats to PCB-mounted ICs may have many sources, three sources are considered most probable:

1. Charged personnel

2. Charged PCB assemblies

3. The combination of a charged person holding a charged PCB Charged Personnel.

Often, when people think of ESD sources, they think of ESD from personnel. Unless wrist straps or other static-preventive measures are used, personnel can become charged due to walking or other motion. When charged personnel contact (or nearly touch) metallic portions of a PWA, ESD will occur. The probability of charged personnel causing ESD damage to an IC is especially severe if the discharge from the person is via a metallic object such as a tool, a ring, a watch band, etc. This hand/metal ESD results in very high discharge current peaks.

Charged PWAs. Printed wire assemblies may also be a source of ESD.

For example, assemblies can become charged when transported along a conveyer belt, during shipping, or when handled by a charged person. If a charged PWA contacts a conductive surface, or is plugged into a conductive assembly, while not in conductive contact with any other source charge, ESD will occur and discharge the PWA.

Charged PWA and Charged Personnel. If a charged person and a PWA are in conductive contact during the ESD event, the ESD will discharge both the person and the PWA. If a person walks across a carpeted floor while in conductive contact with a PWA, the person and the PWA may become charged. If the PWA then contacts a conductive surface, or is plugged into an equipment assembly, while still in conductive contact with the person, charged-PWA-and-person ESD occurs.

Places of Electrostatic Discharge

The places where ESD impinges on a PWA are called discharge points. Discharge points to PWAs can be grouped into three categories:

1. Directly to IC pins

2. Printed circuit board traces between ICs

3. Printed circuit board connector pins

With the possible exception of connector pins, discharge points could be expected to be physically located almost anywhere on the surface of the PCB assembly (PWA).

Integrated Circuit Pins. The pins of a PCB-mounted IC extend above the surface of the board itself. Because of this, an ESD arc can actually terminate on the pins of an IC. In this case, the ESD current will not travel to the device via a PCB trace. However, any trace connected to the IC pin may alter the character of the ESD threat.

PCB Traces. Since ICs do not cover the entire surface of a PCB assembly, a PCB trace may be the nearest metallic point to which an ESD threat may occur.

In this case, the ESD arc will terminate not on an IC pin, but on a PCB trace between IC pins. This is especially true if an ESD-charged electrode (such as a probe tip) is located very close to a PCB trace, at a point equidistant between two ICs. In this case, the ESD current flows to the IC via the PCB trace, modifying the ESD current waveform.

PCB Connector Pins. The connector pins of a PCB assembly are extremely likely to be subjected to ESD when the assembly is being installed in equipment or in a higher-level assembly. Thus, ESD to or from connector pins is often associated with ESD from a charged PCB or a charged PCB-and-person.

Like ESD to traces, ESD to connector pins must flow via a PCB trace to the IC.

PCB Structures That Influence Electrostatic Discharge

In any ESD event, the character of the ESD threat is determined not only by the source of the ESD, but by the ESD receptor, which in this case is the PWA.

When the receptor is a PWA, the path from the discharge point to the IC and the path from the IC to the ground reference are important. Also important is the structure of the ground reference. This structure includes the local ground and external ground reference common to both the IC and the ESD source.

Local Ground Structure. The local ground structure of a PCB is the section of the PCB's ground reference that is part of the PCB assembly itself.

Multilayer PCBs with ground plane layers have the most extensive local ground structures. At the other extreme are PCB assemblies where the only local ground reference is provided by a single ground trace to the IC.

External Ground Structure. The local ground of a PCB may be connected to an external ground. This connection may be intentional (a direct connection to the AC power "green" ground) or unintentional (placing a PWA on a grounded metallic surface). Often PWAs have no metallic connection to any external ground (e.g., during transportation). In this case the only reference to an external ground is via stray capacitance from the PWA to the external ground.

Length of PCB Traces. In addition to the PCB ground structure, lengths of the PCB traces are also important. The trace lengths help determine the impedance and resonant frequency of each of the possible ESD current paths to ICs in a PCB. Studies have shown that ESD conducted to a device through short traces was worse than ESD conducted through long traces. Also the ESD threat was worse for PCBs with no ground plane than for multilayer PCBs using ground and power planes. Finally, the ESD energy threat was consistently worse for PWAs connected to external ground, rather than for floating PWAs. These results show the structure and layout of a PCB have a significant impact on the ESD threat level experienced by devices mounted on the PCB. The ESD threat to devices mounted on a PCB significantly exceeds the threat for unmounted de vices. For a given PCB the sensitivity of the entire assembly is much worse than that of the individual device.

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