Guide to Reliability of Electrical/Electronic Equipment and Products--Electrostatic Discharge and Electromagnetic Compatibility

Home | Articles | Forum | Glossary | Books


1. ELECTROSTATIC DISCHARGE

1.1 What Is Electrostatic Discharge and How Does It Occur?

Electrostatic discharge (ESD), a major cause of failure in electronic components, affects the reliability of electronic systems, including the functioning of an electronic component at any stage-during device fabrication, testing, handling, and assembly; printed circuit board (PCB) assembly and test; system integration and test; and field operation and handling of printed wiring assemblies (PWAs) in the field.

Electrostatic discharge is a charge-driven mechanism because the event occurs as a result of a charge imbalance. The current induced by an ESD event balances the charge between two objects. The ESD event has four major stages:

(1) charge generation, (2) charge transfer, (3) charge conduction, and (4) charge induced damage.

Electrostatic discharge occurs from an accumulation of charges on a surface due to reasons such as contact or friction. The process, called triboelectric charging, can occur when one wearing footwear walks onto a carpeted surface, when an integrated circuit slides through a plastic tray or tube, or during handling of components by handlers or robotic machinery.

In triboelectric charging, there is a transfer of electrons from one surface to the other in which one surface gets negatively charged, due to excess of electrons, and the other gets positively charged, due to a deficiency of electrons in equal measure. Materials differ in their capacity to accumulate or give up electrons.

The increasing miniaturization in electronics and the consequent use of small-geometry devices with thin layers has increased susceptibility to ESD dam age; ESD is a silent killer of electronic devices that can destroy a device in nanoseconds, even at low voltages. Electrostatic discharge causes damage to an electronic device by causing either an excessive voltage stress or an abnormally high current discharge, resulting in catastrophic failure or performance degradation (i.e., a latent defect in the device that may surface later during system operation and cause device failure).

Taking a few simple precautions during device design, assembly, testing, storage, and handling, and the use of good circuit design and PWA layout techniques can minimize the effects of ESD and prevent damage to sensitive electronic components.

Damage is expensive-in the cost of the part; the processes; detection and repair; and in loss of reputation, as well as lost production time. Walking wounded parts can be extremely expensive and although the exact figures are difficult to establish, real overall costs to industry worldwide are certainly measured in terms of many millions, whatever the currency. Once damage has been done, it cannot normally be undone. Therefore, precautions need to be taken from cradle to grave.

1.2 Electrostatic Discharge-Induced Failure Mechanisms

The currents induced by ESD are extremely high. It is the current, directly or indirectly, that causes the physical damage observed in an ESD failure. Direct damage is caused by the power generated during the event. It melts a section of the device causing failure. Indirectly, the current generates a voltage by the ohmic resistance and nonlinear conduction along its path. Small voltages are generated when junctions are operated in a forward bias mode, but large voltages are generated when they are in a reverse bias mode. The reverse bias conduction causes thermal damage at lower current levels because the power dissipation is higher from the higher voltage across the junction. In addition, the voltage generated by this event weakens dielectrics by charge injection. The limiting case for this charge injection is dielectric rupture. Electrostatic discharge can affect an integrated circuit in many ways by causing Thermal overstress leading to melting of the metallization and damage to the various transistor junctions in the device.

Intense electric fields that cause a breakdown of transistor thin gate oxide and the junctions themselves.

Latch-up in the internal circuit of complementary metal oxide semiconductor (CMOS) devices due to parasitic p-n-p-n structures and consequent device failure by electrical and thermal overstresses.

Latent defects caused by ESD may cause the device to malfunction or fail under field conditions. Among the commonly used devices, CMOS ICs are especially susceptible to damage due to ESD.

1.3 Preventing Electrostatic Discharge Damage

Preventing ESD-induced damage in electronic systems requires a multipronged approach that includes application of better design techniques at board and circuit level and observing appropriate precautions during handling of components, testing, assembly, system integration, shipment, and field operation. Protection from ESD looks first to minimize the charge generation and slow the charge transfer by controlling the environment where parts are handled and stored.

Some of the techniques that can be used to reduce ESD-related failures of electronic devices include Use of good circuit design techniques-both by proper choice of components and by using circuit level techniques such as protection networks at critical points in the circuit Use of good grounding and layout techniques. Any charge generated should be discharged to ground in a controlled manner Careful handling of ESD-sensitive components during assembly, production, and testing operations

Use of an ESD-controlled production environment Use of appropriate antistatic packaging Proper shielding of the circuit

All IC manufacturers incorporate various protection circuits on the I/O pins of their ICs. The effectiveness of these protection circuits varies from supplier to supplier and from device type to device type. The fundamental approach in preventing ESD-induced failures is to start by selecting an IC with the appropriate ESD rating. Use a device with a higher ESD immunity that meets the application requirement to reduce the incidence of failures due to ESD. Electromagnetic interference (EMI) and ESD are closely related and can be controlled by using similar methods (ESD can be treated as a subset of EMI). Following are brief descriptions of techniques used to reduce the effects of ESD on electronic systems.

Circuit Design Techniques

High-speed logic transitions cause radiation of high-frequency fields resulting in interference to other devices on the PWA and to sensitive circuits in close proximity. Avoid high-speed devices in the design unless they are needed. But, for today's designs to be competitive requires the use of high speed ICs.

Anticipate problems that could arise in the field and tailor your circuit design appropriately.

Although IC manufacturers provide protective networks consisting of di odes to protect a CMOS device against ESD damage, a higher level of protection using external components is recommended in vulnerable circuit designs.

Use transient suppressor diodes at critical points in the circuit because they respond fast and clamp the voltage to a safe value when an overvoltage transient occurs. Keep the transient suppressor very close to the device terminals. Long leads and long PCB traces have parasitic inductances that cause voltage overshoots and ringing problems (if there is an ESD pulse).

A typical method for suppressing ESD transients, which can be used at the input stage of a circuit, is to slip a ferrite bead on the input lead to the ground.

Use series resistors to limit the rate of discharge.

A good low-impedance ground can divert the energy of the ESD transient efficiently. Maintaining a clean ground holds the key to the proper functioning of many electronic circuits using a mixture of analog and digital circuits.

Proper Printed Circuit Board Design

A properly routed PCB significantly contributes to ESD reduction. Magnetic flux lines exist in all energized cards due to the presence of various components and current flow through the circuit. A large loop area formed by conducting paths will enclose more of the magnetic flux, inducing current in the loop (due to the loop acting as an antenna). This loop current causes interfering fields which affect components in the circuit and the functioning of the circuit (closely routing supply and ground lines reduces loop areas).

Provide a large ground area on a PCB; convert unused area into a ground plane.

Place sensitive electronic components away from potential sources of ESD (such as transformers, coils, and connectors).

Run ground lines between very long stretches of signal lines to reduce loop areas.

Keep sensitive electronic components away from board edges so that human operators cannot accidentally cause ESD damage while handling the boards.

Multilayer boards with separate ground planes are preferred to double-sided boards.

Avoid edge-triggered devices. Instead use level-sensing logic with a validation strobe to improve ESD immunity of the circuit.

360° contact with the shield is necessary to prevent antenna effects (i.e., radiated fields).

Packaging guidelines, as applicable to EMI reduction, should be followed to reduce susceptibility to outside fields and to prevent unwanted radiation that can affect nearby equipment.

At the system level, include a marked wrist strap stud where possible.

Proper Materials for Packaging and Handling

Insulating materials have a surface resistivity greater than 10^14 Ohm/square and retain charge. It is advisable to keep insulating materials such as polyethylene, ceramics, and rubber away from electronic components and assembly areas.

Antistatic materials have a surface resistivity of 10^9 and 10^14 Ohm/square and resist the generation of static electricity. These materials have a short life for reuse and are meant for limited reuse applications, such as storing PWAs and electronic components. In view of the high surface resistivity, connecting this material to ground will not be effective in bleeding off any accumulated charge.

Static dissipative materials have a surface resistivity of 10^5 and 10^9 Ohm/square.

Due to the low surface resistivity, charges on a component can be diverted to ground if the material is used to protect a component against static charge and the static dissipative shield is grounded. Static charges can be generated in such materials by friction, but due to better surface conductivity the charges will spread across the surface. Generally such materials are used to cover floors, tabletops, assembly areas, and aprons.

The surface resistivity of conductive materials is less than 10^5 Ohm/square.

The charge accumulated on the surface of conductive material can be easily discharged to ground. Materials used for packaging electronic components and PWAs are generally plastics with conductive material impregnated.

Assembly and Production Techniques

No item should be allowed inside the ESD protect work area (EPA) that can generate and hold electrostatic charge. Examples include Packaging of polystyrene, untreated cling- and shrink-film, etc., whether for sensitive or non-sensitive parts (this charged packaging can come into contact with sensitive parts) Polystyrene or similar cups or other containers Photocopiers

Sensitive parts should be packaged in low-charging, static-shielding containers (such as bags) when taken out of an EPA.

Sensitive parts should be kept well away from strong electrostatic fields (e.g., CRT monitors) Very strong electrostatic field generators, such as contactors, arc welders and so on, should be kept well away from the EPA.

Any sensitive part brought into the EPA should be resistively grounded or otherwise discharged before use. This can be through contact with a wrist-strapped person, through a resistively grounded (nonmetallic) bench, through ionization, or by other suitable means.

Avoid potential differences between device pins during handling.

CMOS ICs should be stored in antistatic tubes, bins, or conductive foams specially designed for storage. The conductive surfaces in contact with the CMOS devices will bleed off the accumulated charges.

For soldering CMOS devices in PCBs, use a soldering iron in which the tip has a proper ground connection. Tools used to insert or remove CMOS ICs from boards or sockets should also be properly grounded.

Do not insert or remove devices when the circuit power is on to prevent damage due to transient voltages.

Unused communication connectors should be covered with static dissipative material when not in use to prevent charge buildup.

Everyone in an EPA should be resistively grounded. In many cased, the most effective method is by the use of a wrist strap, but for mobile operators where the floor has a good defined resistance to ground, footstraps or conductive footwear may be used except while seated.

Many garments can be static generating. Electrostatic discharge-protective garments should be worn to cover any static-generating clothes in the EPA. These garments need a path to ground, which typically will be through the skin and the wrist strap.

Working surfaces need to be resistively grounded, typically through 1 M-ohm, and to have a surface-to-surface resistance of less than 1000 M-ohm. In few cases, metal surfaces may be used, but in general a point-to-point resistance of greater than 750 K-ohm should be used.

Where grounding through resistance is inappropriate, air ionizers should be considered as a means of preventing static buildup.

Slightly higher humidity conditions provide a means to discharge any charge accumulated to ground and provide protection against static electricity buildup.

Do not use tools with plastic handles (due to the triboelectric effect).

Printed wire assemblies should be stored in antistatic bags.

Antistatic precautions should be observed while handling PWAs in the field.

Electrostatic discharge awareness programs should be conducted periodically.


FIGURE 1 Factors that impact the level of electrostatic discharge to ICs on PWAs.

1.4 The Electrostatic Discharge Threat at the Printed Wire Assembly Level

Much effort has been put into characterizing the impact of electrostatic discharge on individual integrated circuits and on completed equipment such as computers.

However, less time has been spent characterizing the ESD threat to ICs mounted on printed circuit boards. Since completed equipment can only be manufactured by mounting the ICs on subassemblies, the ESD threat to PCB-mounted ICs is an important concern.

Computer simulations have shown that the ESD threat to ICs mounted on PCBs may significantly exceed the threat to unmounted, individual ICs. Factors that impact ESD at the PWA are shown graphically in Figure 1 and are discussed in the following sections.

Sources of Electrostatic Discharge

While ESD threats to PCB-mounted ICs may have many sources, three sources are considered most probable:

1. Charged personnel

2. Charged PCB assemblies

3. The combination of a charged person holding a charged PCB Charged Personnel.

Often, when people think of ESD sources, they think of ESD from personnel. Unless wrist straps or other static-preventive measures are used, personnel can become charged due to walking or other motion. When charged personnel contact (or nearly touch) metallic portions of a PWA, ESD will occur. The probability of charged personnel causing ESD damage to an IC is especially severe if the discharge from the person is via a metallic object such as a tool, a ring, a watch band, etc. This hand/metal ESD results in very high discharge current peaks.

Charged PWAs. Printed wire assemblies may also be a source of ESD.

For example, assemblies can become charged when transported along a conveyer belt, during shipping, or when handled by a charged person. If a charged PWA contacts a conductive surface, or is plugged into a conductive assembly, while not in conductive contact with any other source charge, ESD will occur and discharge the PWA.

Charged PWA and Charged Personnel. If a charged person and a PWA are in conductive contact during the ESD event, the ESD will discharge both the person and the PWA. If a person walks across a carpeted floor while in conductive contact with a PWA, the person and the PWA may become charged. If the PWA then contacts a conductive surface, or is plugged into an equipment assembly, while still in conductive contact with the person, charged-PWA-and-person ESD occurs.

Places of Electrostatic Discharge

The places where ESD impinges on a PWA are called discharge points. Discharge points to PWAs can be grouped into three categories:

1. Directly to IC pins

2. Printed circuit board traces between ICs

3. Printed circuit board connector pins

With the possible exception of connector pins, discharge points could be expected to be physically located almost anywhere on the surface of the PCB assembly (PWA).

Integrated Circuit Pins. The pins of a PCB-mounted IC extend above the surface of the board itself. Because of this, an ESD arc can actually terminate on the pins of an IC. In this case, the ESD current will not travel to the device via a PCB trace. However, any trace connected to the IC pin may alter the character of the ESD threat.

PCB Traces. Since ICs do not cover the entire surface of a PCB assembly, a PCB trace may be the nearest metallic point to which an ESD threat may occur.

In this case, the ESD arc will terminate not on an IC pin, but on a PCB trace between IC pins. This is especially true if an ESD-charged electrode (such as a probe tip) is located very close to a PCB trace, at a point equidistant between two ICs. In this case, the ESD current flows to the IC via the PCB trace, modifying the ESD current waveform.

PCB Connector Pins. The connector pins of a PCB assembly are extremely likely to be subjected to ESD when the assembly is being installed in equipment or in a higher-level assembly. Thus, ESD to or from connector pins is often associated with ESD from a charged PCB or a charged PCB-and-person.

Like ESD to traces, ESD to connector pins must flow via a PCB trace to the IC.

PCB Structures That Influence Electrostatic Discharge

In any ESD event, the character of the ESD threat is determined not only by the source of the ESD, but by the ESD receptor, which in this case is the PWA.

When the receptor is a PWA, the path from the discharge point to the IC and the path from the IC to the ground reference are important. Also important is the structure of the ground reference. This structure includes the local ground and external ground reference common to both the IC and the ESD source.

Local Ground Structure. The local ground structure of a PCB is the section of the PCB's ground reference that is part of the PCB assembly itself.

Multilayer PCBs with ground plane layers have the most extensive local ground structures. At the other extreme are PCB assemblies where the only local ground reference is provided by a single ground trace to the IC.

External Ground Structure. The local ground of a PCB may be connected to an external ground. This connection may be intentional (a direct connection to the AC power "green" ground) or unintentional (placing a PWA on a grounded metallic surface). Often PWAs have no metallic connection to any external ground (e.g., during transportation). In this case the only reference to an external ground is via stray capacitance from the PWA to the external ground.

Length of PCB Traces. In addition to the PCB ground structure, lengths of the PCB traces are also important. The trace lengths help determine the impedance and resonant frequency of each of the possible ESD current paths to ICs in a PCB. Studies have shown that ESD conducted to a device through short traces was worse than ESD conducted through long traces. Also the ESD threat was worse for PCBs with no ground plane than for multilayer PCBs using ground and power planes. Finally, the ESD energy threat was consistently worse for PWAs connected to external ground, rather than for floating PWAs. These results show the structure and layout of a PCB have a significant impact on the ESD threat level experienced by devices mounted on the PCB. The ESD threat to devices mounted on a PCB significantly exceeds the threat for unmounted de vices. For a given PCB the sensitivity of the entire assembly is much worse than that of the individual device.

2. ELECTROMAGNETIC COMPATIBILITY

2.1 Introduction to Electromagnetic Compatibility

Electromagnetic compatibility (EMC) deals with the proper functioning of electronic equipment in an electromagnetic interface environment and compliance with various regulatory agency equipment interference generating and control requirements ("don't interfere with others; don't be interfered with; don't interfere with yourself"). Electromagnetic compatibility has been called the good housekeeping of electrical circuit design. It is applicable in all industries where electrical design occurs.

Electromagnetic compatibility is all about designing products that function within their intended environments in electromagnetic symbiosis with other products that must share the same environment. Products must not cause other products to malfunction or, in the most basic sense, disrupt communications. Chaos would result.

Today, products must be capable of unimpaired operation in an ever-changing electromagnetic world. Immunity to external electromagnetic events is no longer a design advantage; it is a product requirement. Many subassemblies and components that are used in the design of new products create their own micro electromagnetic environments which can disturb normal operation of nearby circuits. Learning to identify, avoid, and/or troubleshoot these electromagnetic problems is essential.

National regulatory agencies first promoted EMC because of concern over communications interference. Satisfying these agencies' requirements is still very much an essential task. The list of countries that have legislated mandatory compliance to EMC limits grows each year. Additionally, many country regulators are requiring EMC compliance reports be submitted for review and approval.

Laboratory accreditation by country authorities is another requirement that must be addressed.

Regardless of the mandatory requirements for compliance to EMC standards, competitive pressures and customer demands for robust products are good justification for improving EMC designs.

Electromagnetic Interference

Electromagnetic interference (EMI) occurs when an electrical or electronic de vice's normal intended operation is compromised by another electrical or electronic device's usage.

Conducted EMI is caused when an interfering signal is propagated along power or signal lines. An example of conducted interference would be when your television goes fuzzy at the time your refrigerator compressor turns on.

Radiated electrical field (E-field) interference is an electric field that is propagated through the air. This field then couples into a receptor. An example of E-field interference would be the noise you hear on your portable telephone when you bring it near your computer.

Radiated magnetic field (H-field) interference is a magnetic field that is propagated through the air. An example would be two computer monitors placed sufficiently close so that their displays appear to bounce and distort.

Recapping the previous section, electrostatic discharge occurs in the following manner: An object (usually conductive) builds up an electrostatic charge through some form of motion or exposure to high velocity air flows. This charge can be many kilovolts. When the charged object comes in contact with another (usually conductive) object at a different charge potential, an almost instantaneous electron charge transfer (discharge) occurs to normalize the potential be tween the two objects, often emitting a spark in the process. Depending upon the conductivity of the two objects, and their sizes, many amperes of current can flow during this transfer. Electrostatic discharge is most often demonstrated by shuffling across a carpet and touching someone, causing the signature electrical zap to occur. Confusion occurs with plastic insulators that can become charged to many kilovolts, but because of their high resistance dissipate low current levels very slowly.

Example of EMI-Caused Problems. Many switching power supplies are operating with a fundamental switching frequency between 100 kHz and 1 MHz.

These designs emit very high electrical and magnetic fields and may disturb sensitive circuits by coupling noise. Digital designs using high-speed ICs (such as microprocessors and memories) with their fast rising and falling edges cause the same problems but at a more severe level. The microprocessor is by far the largest source of electromagnetic energy. Containing radiated and conducted emissions at the source (the CPU package) would make the system design easier for computer original equipment manufacturers (OEMs). To comply with FCC regulations, the system must be tested for emissions at up to five times the CPU operating frequency or 40 GHz, whichever is lower. This is necessary because of the harmonics that are generated from the base CPU frequency. The main component of EMI is a radiated electromagnetic wave with a wavelength that gets smaller as the frequency increases. Disk drive read/write heads are occasional victims. The trouble often manifests as high error rates or retries slowing data transfer rather than exhibiting a complete failure.

Electrostatic discharge sensitivity is often an elusive problem to solve, but most times it is the result of a compromised ground system. An example would be a product with high sensitivity to physical contact by operators such as a semiconductor wafer handler that randomly stops.

Cable television reception can easily be degraded by a pigtail connection of the shield to the input signal connector and further degraded by a nearby computer, monitor, or microwave oven.

Automotive electronic ignition can be both a nuisance to radio and a victim of radio signals. Some time back Porsches were known to be sensitive to certain ham radio frequencies, and the knowledgeable fun-loving EMC types would key their microphones as they neared such vehicles on the highways.

Cellular phones don't work so well in tunnels or in mountainous terrain.

Electromagnetic Compatibility Basics

Recognizing EMC problems in a design can be straightforward or extremely subtle. Focusing on problem avoidance by practicing some simple yet effective design rules will minimize or eliminate the need for corrective efforts late in the development cycle. These EMC design practices are applicable throughout all aspects of electrical/electronic product design.

Fourier analysis shows that the signals most focused on in EMC design are the clock and clock harmonic signals. This is because the emitted signals detected are continuous and periodic, typically square waves. The Fourier series model for a square or trapezoidal wave is a sine wave expansion of the fundamental frequency, explaining why digital signals are really complex analog signals.

This is an important point to remember in EMC design. It is clock and clocklike signals that cause most common-mode noise. Random signals, such as data, do not cause the emissions that are measured. However, we must still be concerned with these signals from a signal integrity perspective.

Common Mode Noise. Common mode noise is undesirable signals or changes in signals that appear simultaneously and in phase at both input terminals and/or at all output terminals. These signals will be equal in amplitude and phase when measured at the input or outputs terminals, but the input amplitude may not equal the output amplitude because of the different characteristics of the common mode filters located at the input and output terminals. Most emissions-related problems are common mode.

Common mode filters must act on all conductors in an input or output circuit to be effective. A common toroidal core is usually included in the design.

Inside the product, both the power supply and the printed circuit board(s) will generate their own common mode noise profiles. Note: if the power supply output return (ground) and printed circuit board ground are conductively tied to chassis through a very low impedance bond, the internal common mode noise will be greatly reduced by the absence of a dV/dt between return current paths and chassis.

Differential Mode Noise. Differential mode noise is an undesirable signal appearing on the input or output terminals external to the enclosure versus one another and is measured with respect to chassis (ground). Any one of these signal measurements (noise) is not equal in amplitude or phase to any other one. Differential mode noise may also occur internally within the product.

Differential filtering is usually easy to implement, typically a simple inductive (L) or capacitive (C) component, assuming the ground system is working properly.

Ferrites. A ferrite is an EMI suppression component used to provide broadband, low-Q, and high-frequency impedance. Ferrites have both reactive (inductive) and lossy (resistive) properties. They have high resistivity and are nonconductive at low voltage.

Ferrites consist of sintered fine manganese-zinc or nickel-zinc ferrite powders that exhibit magnetic properties related to the frequency at which they are excited. By varying the permeability of these powders, it is possible to change the frequency response curve of ferrites. When a high-frequency current passes through the ferrite, these powders will attempt to reorient themselves much like what happens when a magnet is placed under iron particles on a piece of paper.

Since the ferrite powder particles cannot move in place, the high frequency energy they absorb is converted into heat. Ferrites are very low maintenance and resistant to corrosion, rust, chemicals, and heat in the range of electronic circuits.

Ferrites are frequently used on cables for common mode noise reduction.

They may also be designed into printed circuit boards as common mode I/O filters for unshielded I/O cables or in power or signal lines as differential or common mode filters. When used on cables, concerns for permanency must be addressed. A ferrite can become dislodged, misplaced, or forgotten during maintenance. Use design practices to avoid the need for ferrites on cables whenever possible.

Shielding. Electromagnetic shielding is the use of conductive barriers, partitions, or enclosures to improve a product's EMC performance. Shields are a design tool that completes an enclosure to meet EMC design goals and should not be considered to be a band-aid solution.

Shielding solutions may be applied internally to the product, on cables, or as the external enclosure. Parts of the external enclosure that form a shield require continuous conductive connections along their intersecting surfaces. Addition ally, they must bond to chassis (ground) using similar low-impedance techniques.

These connections are important to reduce radiated emissions, provide protection from externally radiated influences, and increase immunity to electrostatic discharge events.

Local shields may be valuable to reduce the EMI effects from noise sources that may otherwise disrupt normal use of the product or benefit the overall EMC performance.

Shields provide a conductive path for high-frequency currents, minimize the number of apertures, and function as design seams for continuous conductive interfaces. Conductive gaskets should be used on doors and access panels that are part of shielding. Noncontinuous conductive seams along enclosure shields have the tendency to form a dV/dt at the gap and radiate from the slot antenna formed.

Note: it is advisable to derate vendor claims by at least 10 dB since the tests are typically conducted in ideal situations.

Bonding. Bonding is the low-impedance interconnection to conductive ground potential subassemblies (including printed circuit board grounds), enclosure components to each other, and to chassis. Low impedance is much more than an ohmmeter reading 0.0 ohm. What is implied here is continuous conductive assembly to provide high-frequency currents with continuous conductive surfaces.

Some practical design hints to ensure proper bonding include the following:

Painted, dirty, and anodized surfaces are some of the biggest problems to avoid up front. Any painted surfaces should be masked to prevent overspray in the area where bonding is to occur. (The exception is where conductive paints are used on plastic enclosures; then paint is needed along the bond interface.) Screw threads are inductive in nature and cannot be used alone to assure a suitable bond. They are also likely to oxidize over time.

Care should be used to avoid the use of dissimilar metals. Galvanic corrosion may result in very high-impedance bonds.

Conductive wire mesh or elastomer gaskets are very well suited to assure continuous bonds over long surface interfaces.

Choose conductive platings for all metal surfaces.

Designs that take advantage of continuous conductive connections along surface interfaces that are to be bonded are the most effective to support high-frequency currents. Sharp angle turns along a bond should be avoided since they will cause high-frequency current densities to in crease at such locations, resulting in increased field strengths.

Loop Control. Designers need to consider that current flows in a loop and that the return current tries to follow as close to the intentional current as possible, but it follows the lowest impedance path to get there. Since all these return cur rents are trying to find their different ways back to their source, causing all kinds of noise on the power plane, it is best to take a proactive multipronged design approach. This includes designing an intentional return path (i.e., keeping to one reference plane), preventing nets from crossing splits in adjacent planes, and inserting bypass capacitors between planes to give the return current a low impedance path back to the source pin.


FIGURE 2 Loops and loops currents.

Often in CPU server designs (see Fig. 2) the overall loop and loop currents are of the same size, but individual loop areas are dramatically different. It is the loop area that is the cause for concern with respect to ground loops, not the loop. It is also important to note that a ground plane has an infinite number of ground loops.


FIGURE 3 Distributing the current across a PWA.

Each small ground loop in the lower block is carrying a loop current IRF.

What is happening is that the loop currents cancel each other everywhere except along the perimeter of the loop. The larger ground loop also carries loop current IRF but has a greater loop area. Larger loops tend to emit and cause interference and are also more susceptible to disruption from external electromagnetic fields.

This is why EMC design of two-sided printed circuit boards is improved by forming grids with both power and ground. The loop area can also be reduced by routing cables along ground potential chassis and enclosure walls.

Skin Effect. Skin effect is the depth of penetration of a wave in a conducting medium. As frequency increases the "skin depth" decreases in inverse proportion to the square root of the frequency. Thus, as frequency increases, current flows closer to the surface of a conductor. This is one reason why bonding of conductive surfaces requires careful attention. It is desirable to provide as much continuous surface contact as possible for high-frequency currents to flow unimpeded.

Current Density. The current density J in a wire of cross-sectional area A and carrying current I is J _ I A

Thus, as the area increases, the current density will decrease, and the current in any one section of this area will be low.

Bonding and shielding attempt to distribute high-frequency return currents throughout the surfaces of the ground system. When this is completed, the high-frequency current density (dI/dt) is reduced to very low levels and results in a near equipotential surface, causing dV/dt to approach zero. By minimizing the current density, the generated field strengths can be reduced to a minimum. Using a distributed, low-impedance conductive current path to accomplish this is a very effective, economical, and reliable design approach.

Distributed Current Path. As IRF crosses any boundary we know that it is flowing on the surface of the conductors. If the path impedance ZP at any contact is low, and we have many contacts, then we have a distributed current path (Fig. 3). The best way to keep high-frequency currents from radiating is to maintain a distributed low-impedance current path where currents can freely flow.

This is one of the design variables that are controlled and is effective, cost efficient, and very reliable.

2.2 Electromagnetic Compatibility Design Guidelines

Grounding

The grounding system is the backbone to EMC. If its integrity is preserved, a given product will achieve best EMC/ESD performance, lowest common mode noise levels, best EMC cost efficiency, and competitive advantage through customer satisfaction. Robust grounding is the design practice of conductively connecting all ground referenced circuitry and the chassis together through very high-conductivity, low-impedance (broadband) bonds. This approach attempts to establish a near equipotential electrical reference (system) ground by recognizing and leveraging from the fact that all grounds are analog.

In a grounding system, the "green wire" has no essential role in EMC de sign. Its sole role is to provide a current path to ground in the event of a fault condition that would result in a shock hazard. This conductor is of relatively high impedance at high frequency and looks much like an inductor. For EMC, a given product's radiated emissions profile should be unaffected by the presence of the green wire.

The conducted emissions profile may be impacted by the presence of the green wire if the design depends upon Y (line to ground) capacitors to reduce conducted emissions because Y capacitors increase leakage current in the green wire. A common mode choke used in the supply input can reduce conducted emissions without increasing leakage current. Since one generally designs with leakage current limits in mind, most input filter designs will use both Y capacitors and common mode chokes.

X (line-to-line or line-to-neutral) capacitors are used in the input filter circuit to reduce differential mode conducted emissions. X capacitors do not affect leakage current.

An improperly attached green wire can cause the power cable to radiate emissions. If the green wire loop is substantially long, it can pick up internal noise and act as a radiating antenna outside the enclosure. Design hint: keep the green wire within the product as short as possible (one inch long is a good rule of thumb) and routed next to chassis to reduce loop area.

So what is this equipotential system reference? Ground continuity is pro vided along as many interfaces as is reasonably possible, so that multiple low impedance current paths are joined together (Fig. 4). The result is a distributed low-impedance ground system. High-frequency currents flow on the surface of these paths (skin effect) and have very low current densities. If the dI/dt approaches zero, then the dV/dt will also approach zero.

This begs the question at what potential is ground. If it is equipotential, who cares? The less dependent our system is on the potential of the ground system, the better it will perform. A satellite has an excellent ground system yet it has no conductive connection to earth. The same applies to a handheld, battery-powered electronic device or a large, floor-standing, earthquake-anchored, AC-powered electronic system.


FIGURE 4 Equipotential system provides ground continuity across many interfaces.

Electrostatic discharge events rarely disturb a product with a robust ground system. This is because the entire product responds using its very near equipotential reference to ground. Upon discharge, the high-frequency, high-current event uniformly distributes its charge throughout the ground system. If the product has a green wire, the charge will drain off to earth, otherwise the ground system of the still operating product will remain charged until it encounters a discharge path.

Chassis/Enclosures

The chassis or enclosure forms the outer protective and/or cosmetic packaging of the product and should be part of the EMC design. Metal enclosures should use plated protective coatings, but they must be conductive. Do not use anodized metals as they are nonconductive.

Design hints for metal enclosures:

1. Design assemblies such that connecting surfaces make a continuous conductive connection (bond) over the full length of interconnecting intersections. Seams of external covers should overlap. Hinges do not make suitable bonds. Conductive gaskets are often needed.

2. Select materials to minimize galvanic corrosion potential and assure that bonds remain intact over the product life.

3. Do not rely on mu metal; it is minimally effective at best.

Plastic enclosures may need to have a conductive coating if relied upon to reduce radiated emissions. Design hints for plastic enclosures:

1. Conductive coatings require clean plastic surfaces, well-radiused intersecting planes, and supports to allow coating to adhere. Continuous conductive mating assembly is required.

2. Coatings work well, but can be sensitive to abrasion and wear due to multiple assembly operations.

Power entry enclosure guidelines:

1. The green wire should terminate as immediately as possible once inside the enclosure. Typically within one inch. Minimize any loop area by routing next to chassis.

2. Power line filter modules should bond to the enclosure at the entry or as close as possible. A filter's output leads must be physically routed away from the input leads. If using a power filter with an integral IEC connector for a power cable, the filter must bond to the chassis 360° around their common interface. If an AC or DC input power cable is radiating with the filter in place, you may just need to add a common mode (common core toroid) ferrite on the leads exiting the filter (not to include the green wire).

3. At peripheral interfaces connector shells for shielded I/O cables must make a continuous 360° conductive bond with the enclosure where they penetrate the enclosure.

4. Unshielded interface cables will require some form of I/O filtering to prevent the I/O cable from becoming a radiating antenna. I/O filters, when used must be very near the I/O connector.

Power Supplies

Because of the need for high-efficiency power supply designs, the switching power supply is probably the most common technology encountered today.

Switching supplies emit very strong electrical and magnetic fields. These can be minimized by using a ferrite common mode core on the AC input leads (not including the green wire) and by bonding the output return(s) to chassis.

Linear and ferroresonant supplies do not switch at high frequencies and are therefore not a radiated electric field concern. Their magnetic fields are, how ever, very strong and can be disruptive. A metal enclosure or localized barrier usually contains this problem. Generally these devices only require input filtering if they have high-frequency loads.

When using off-the-shelf power input filter modules, place them as near to the power entry as possible, and provide them with a good bond to chassis.

If the AC power cable is radiating, try placing the AC input leads through a ferrite core (this is a high-frequency common mode filter). The green wire is never filtered, but instead routed next to chassis and attached to the ground lug using the shortest wire length possible (maximum 1 in. long).

The small modular DC/DC converters available today are switching at speeds from 100 kHz to over 1 MHz and because of their very fast rise times can contribute to both conducted and radiated emissions. The output returns should always be bonded to ground. If the input is safety extra low voltage (SELV), the input return should also be bonded to ground. A high-frequency filter capacitor should be placed at the input and output terminals. Also an input choke is good practice (differential if grounded return, otherwise common mode).

Printed Circuit Boards

Printed circuit boards can be safely designed for EMC by adhering to some basic rules. For multilayer PCBs,

1. Provide a perimeter conductive band around all layers within the printed circuit board except the ground (return) layers. These ground bands are of arbitrary width, but are normally 0.25 in. wide. Where a conflict exists with trace routing or components, the ground band may be necked down to a narrower dimension or selectively omitted to avoid component conflicts. The external perimeter ground bands are to be free from solder mask, if possible, or masked with a pattern that exposes conductive access. This provides a means for persons handling the completed printed circuit assembly to bring the board to their electrostatic potential by accessing ground first, thus minimizing any ESD damage possibilities.

2. Conductively connect all perimeter ground bands in every layer to each other and to the ground plane(s) using vias stitched at an approximate 0.250-in. pitch, assuming 0.020-in. diameter vias. Note: vias can be solder pasted to accomplish the desired conductive access on each external surface.

3. The mounting means for the printed circuit board shall provide a low impedance bond between the printed circuit board's ground and chassis. Standoff's are higher impedance than L brackets. Keep the skin effect in mind.

4. There shall be no isolations in ground planes, no traces, no moats, and no slots or splits. Voids are only allowed in conjunction with the use of a filter at an I/O connector. The ground plane is otherwise a complete copper plane with via holes or connects.

5. Where a printed circuit board has more than one ground plane, all connections to ground shall connect to every ground plane.

6. Some devices (components) are inherently noisy emitters, and when they are used it may be necessary to construct a Faraday enclosure (a conductive cage bonded to ground) around them. The printed circuit board's ground may be used to provide one of the six sides of the enclosure by designing a continuous, exposed, conductive outline (via stitched) ground band around the component's perimeter on the printed circuit board, much like the perimeter ground. The remainder of the enclosure can then be attached to this exposed conductive out line on the printed circuit board to form the remainder of a Faraday enclosure around the offending component.

7. For clock oscillators, provide a ground pad in the shape of the foot print of the clock oscillator that is located directly beneath the oscillator. This ground pad should then be tied to the ground pin. This pad provides a "keep-out" that cannot be accidentally violated when routing traces.

8. Clock and high-speed signal traces shall be routed on internal layers whenever possible (sandwiched between power and ground planes).

For example, with a four-layer printed circuit board it is preferred to route clock traces nearest the ground planes as much as possible, al though it is also acceptable to route next to the voltage plane.

9. If an I/O port is intended for use with a shielded cable, then the I/O connector shell must be conductively connected to the printed circuit board's ground plane(s).

10. When an I/O port is intended for use with unshielded cable, an I/O filter is required, and it must include a common mode stage that incorporates a common core shared by all I/O lines. The filter must be physically located as close to the I/O connector as possible. Traces to the input side of the filter cannot cross traces to the output side of the filter on any layer. Traces from the filter output to the I/O connector should be as direct as possible. A void is then designed in all layers (including the power and ground planes) of the printed circuit board between the filter input connections and the I/O connector pins.

No traces may be routed in the void area except for those going from the filter to the I/O. A minimum separation of five trace widths of the I/O signal lines must be maintained between the void edges and the I/O traces. The void represents a transition zone between the filter on the printed circuit board and free space. The intent is to avoid coupling noise onto the filtered I/O lines.

Design Rules for Single- and Double-Sided PCBs. Single- and double sided printed circuit boards do not enjoy the luxury of a continuous power and ground plane, so the preferred practice is to create two grids, thus simulating these planes using interconnected small loops. The method of doing this is to run traces in one direction on the top side of the board and perpendicular traces on the bottom side of the board. Then vias are inserted to conductively tie the traces of each, forming a power grid and a ground grid at the intersection of these respective traces if viewed perpendicular to the board plane. Power and ground grid line widths should be at least five times the largest signal trace widths.

The ground must still bond to the chassis at each mounting, and the perimeter band is still preferred.

With single-sided boards, the grid is formed using one or both sides of the board using wire jumpers soldered in place versus traces on the opposite side and via bonds.

Clock lines are usually routed with a ground trace (guard band) on one or both sides following the entire clock trace lengths and maintaining very close proximity to the clock trace(s). Guard bands should be symmetrical with the clock trace and should have no more than one trace width between the clock and guard traces.

All other rules previously described are essential and should be observed.

Grounds, Voids Moats, and Splits It is important that robust grounding be used. The reason for repetition is that there are EMC design approaches that conflict with one another. Always design the ground system first. Selectively emphasize the use of voids, and never moats, splits, nor slots in the ground plane.

Voids are a means of providing a transition for unshielded cable I/O's.

Voids permit one to substantially reduce capacitive coupling of internal common mode noise to unshielded wire that should otherwise behave as transmitting antennas. There is no other EMC use for voids in printed circuit boards.

Moats are a recent concept that has been overused. If the common mode noise has been reduced to the lowest levels by tying the ground return and chassis together with low-impedance bonds, one must question why common mode noise should be increased by allowing a dV/dt in the ground. The use of moats may have some benefits, but only if done in the voltage plane and only if the signal traces to and from the moated components are routed over or under the bridge joining the moated voltage section. Never moat a ground (return) plane.

Splits or slots should never be considered in a ground plane. Splits or slots cause an impedance discontinuity seen by a trace with respect to ground, thereby distorting the desired signal quality. Additionally, they encourage a dV/dt be tween the ground reference on either side of the gap, affecting radiated emissions and assuring increased sensitivity to an external event such as ESD. Splits or slots do not belong anywhere in ground planes.

Component Placement

Component placement requires that careful attention be given to the performance and sensitivities of components to be used in a design. From an EMC perspective it is desirable to arrange components in zones so that related components are placed near the components they interact with. It is important to segregate sensitive analog components that might disrupt one another's performance. In the same way, power components can also be grouped so that their higher fields will not interact with other components or subassemblies. However, from other perspectives, such as thermal and mechanical design, it is necessary to distribute both the heat-generating components and the massive (physical size and weight) components across the PWA to prevent hot spots (large thermal gradients across the PWA) and mechanical stress (leading to physical damage), respectively.

It is important to ensure that traces are routed such that sensitive signal traces are routed adjacent to the ground plane and physically separated from all other traces (especially high-speed digital signals) by at least five trace widths.

Remember that the magnetic properties of high-speed current flow will cause return currents to follow the mirror image of a trace in the ground plane.

High-frequency capacitors need to be placed at every oscillator and IC, and often several may be needed around larger arrays or application-specific integrated circuits (ASICs). The choice of capacitor value will depend upon the operating frequencies and the rise times of switching signals. Additionally, bulk electrolytic capacitors should be distributed throughout the board to supply large local demands for current and mitigate voltage sag.

Let's consider the issue of resistor-capacitor (RC) time constant and using capacitors to slow rise time. While it is true that in order for signals to propagate faster, the values of the capacitor or series termination resistor need to be lower so that the rise time is shorter, the circuit designer needs to remember the noise comes from uncontrolled current. The shorter the rise time, the higher the dI/dt of the signal, allowing higher frequency content noise. Timing budgets might be met, but EMI can be running rampant. Tuning the rise time so that it's the mini mum required to make timing requirements minimizes the noise current created.

Take the example of a trapezoidal signal. At frequencies beginning at 1/p (t _ r) where t is the pulse width, the spectrum of the waveform falls off at _20 dB/ decade. For frequencies above 1/p (t _ r), where (t _ r) is the rise time, the fall-off is _40 dB/decade, a much greater level of attenuation. In order to reduce the spectral content quickly, the frequency of the _40-dB/decade region needs to be as low as possible, and pulse width and rise times need to be as large as possible, again trading this off with the timing budgets.

Clock terminations are essential at the origin and at every location where a clock signal is replicated. Whenever possible, a series of damping resistors should be placed directly after a clock signal exits a device. While there are many termination methods-pull-up/pull-down resistors, resistor-capacitor networks, and end series resistor terminations-the use of series resistors at the source terminations are preferred. The series clock termination resistor values are usually in the range of 10 to 100 ohm. It is not advisable to drive multiple gates from a single output since this may exceed the capability to supply the required load current.

Similarly, series terminations are effective in high-speed data or address lines where signal integrity is an issue. These resistors flatten the square wave by diminishing the overshoot and undershoot (ringing). Occasionally a component or subassembly will interfere with other parts of a product or will require supple mental shielding to achieve design goals. Local shields are effective in situations where there are high levels of magnetic or electric field radiation. These shields should be bonded to ground. Local shields may also be used to supplement the shielding effectiveness of the enclosure, thereby reducing overall radiated emissions.

Conductive shells of I/O connectors intended to mate with shielded cables must be conductively bonded to the printed circuit bond ground plane, and the conductive connector shell must bond to the enclosure 360° around as it exits the enclosure.

Cables

Cables can affect both the emissions and desired signal integrity characteristics.

The following are some EMC design hints for cables:

1. Shielded cables rely upon 360° shield terminations at each end of the cable and at the devices to which they attach.

2. Ribbon cables may increase or alternate the number of ground conductors to reduce crosstalk. Shields on ribbon cables are difficult to terminate to ground to be beneficial at high frequencies.

3. Whenever possible route cables next to chassis or ground potential surfaces to minimize noise coupling or emissions. Also route cables away from other cables or circuits that may be noisy or which carry large currents. It is a good practice to route signal cables away from AC power cables.

4. Ferrites can be added to cables to reduce common mode noise. It is important to first attempt to correct the underlying cause for wanting to use a ferrite. Is it because a shielded cable has a rubber grommet between the cable shield and the connector housing? Do you have pig tail shield termination? Make sure that the ferrite solution is maintain able and secure.

5. At lower frequencies, twisting cable leads reduces lower frequency common mode noise.

6. Fiber optic cables are not susceptible to EMI, nor do they radiate EMI.

Bonding I/O connectors intended for use with shielded cables must make a 360° bond with the enclosure at the place where they exit the enclosure. Where possible, choose connectors that can be easily bonded to the enclosure without leaving any unbonded gaps. The concept of 360° bonds must be carried through to include the mating connector shell, its housing, and its subsequent bond with the cable shield exactly at the cable's exit from the housing and similarly at the other end of the cable. Shields must be terminated in this manner at both ends of a cable to be effective. Otherwise the cable will radiate.

Some of the other connector styles commonly in use do not readily lend themselves to this type of bond because of their physical designs. When this occurs a conductive bond may have to be provided by a thin spring finger-like gasket or some other gasket cut to tightly fit the connector ground shell and reach the enclosure.

Printed circuit board grounds must achieve a good low-impedance bond with the enclosure along the I/O boundary exiting the enclosure.

ACKNOWLEDGMENT

The material in Section 2 courtesy of EMC Engineering Department, Tandem Computer Division, Compaq Computer Corporation.

FURTHER READING

1. Archambeault B. Eliminating the myths about printed circuit board power/ground plane decoupling. Int J EMC, ITEM Publications, 2001.

2. Brewer R. Slow down-you're going too fast. Int J EMC, ITEM Publications, 2001.

3. Brewer RW. The need for a universal EMC test standard. Evaluation Engineering, September 2002.

4. Dham V. ESD control in electronic equipment-a case study. Int J EMC, ITEM Publications, 2001.

5. Gerfer A. SMD ferrites and filter connectors-EMI problem solvers. Int J EMC, ITEM Publications, 2001.

6. ITEM and the EMC Journal, ITEM Publications.

7. Mayer JH. Link EMI to ESD events. Test & Measurement World, March 2002.

8. Weston DA. Electromagnetic Compatibility Principles and Applications. 2nd Ed. New York: Marcel Dekker, 2001.

Top of Page PREV.   NEXT Article Index HOME