|Home | Articles | Forum | Glossary | Books|
3. Monolithic device elements
Now we shall consider the various elements that make up an integrated circuit, and some of the steps in their fabrication. The basic elements are fairly easy to name-transistors, resistors, capacitors, and some form of inter connection. There are some elements in integrated circuits, however, which do not have simple counterparts in discrete devices. We shall consider one of these, charge transfer devices, in Section 4. Discussion of fabrication technology is difficult in a guide of this type, since device fabrication engineers seem to make changes faster than typesetters do! Since this important and fascinating field is changing so rapidly, the reader should obtain a basic understanding of device design and processing from this discussion and then search out new innovations in the current literature.
3.1 CMOS Process Integration
A particularly useful device for digital applications is a combination of n-channel and p-channel MOS transistors on adjacent regions of the chip. This complementary MOS (commonly called CMOS) combination is illustrated in the basic inverter circuit of FIG. 4a. In this circuit the drains of the two transistors are connected together and form the output, while the input terminal is the common connection to the transistor gates. The p-channel device has a negative threshold voltage, and the n-channel transistor has a positive threshold voltage. Therefore, a zero voltage input (Vin = 0) gives zero gate voltage for the n-channel device, but the voltage between the gate and source of the p-channel device is -VDD. Thus the p-channel device is on, the n-channel device is off, and the full voltage VDD is measured at Vout (i.e., VDD appears across the nonconducting n-channel transistor). Alternatively, a positive value of Vin turns the n-channel transistor on, and the p-channel off. The output voltage measured across the "on" n-channel device is essentially zero. Thus, the circuit operates as an inverter-with a binary "1" at the input, the output is in the "0" state, whereas a "0" input produces a "1" output. The beauty of this circuit is that one of the devices is turned off for either condition. Since the devices are connected in series, no drain current flows, except for a small charging current during the switching process from one state to the other. Since the CMOS inverter uses ultra little power, it is particularly useful in applications such as electronic watch circuits that depend on very low power consumption. CMOS is also advantageous in ultra large-scale integrated circuits (Section 5), since even small power dissipation in each transistor becomes a problem when millions of them are integrated on a chip.
The device technology for achieving CMOS circuits consists mainly in arranging for both n-and p-channel devices with similar threshold voltages on the same chip. To achieve this goal, a diffusion or implantation must be performed in certain areas to obtain n and p regions for the fabrication of each type of device. These regions are called tubs, tanks, or wells (FIG. 5). The critical parameter of the tub is its net doping concentration, which must be closely controlled by ion implantation. With the tub in place, source and drain implants are performed to make the n-channel and p-channel transistors. Matching of the two transistors is achieved by control of the surface doping in the tub and by threshold adjustment of both transistors by ion implantation.
Including bipolar transistors in the basic CMOS technology allows flexibility in circuit design, particularly for providing drive currents. The combination of bipolar and CMOS (called BiCMOS) provides circuits with increased speed.
Attention must be paid in CMOS designs to the fact that combining n-channel and p-channel devices in proximity can lead to inadvertent (parasitic) bipolar structures. In fact, a p-n-p-n structure can be found in FIG. 4b, which can serve as an inefficient but troublesome thyristor (see Section 10). Under certain biasing conditions the p-n-p part of the structure can sup ply base current to the n-p-n structure, causing a large current to flow. This process, called latchup, can be a serious problem in CMOS circuits. Several methods have been used to eliminate the latchup problem, including using both n-type and p-type tubs, separated by trench isolation (FIG. 6). The use of two separate tubs (wells) also allows independent control of threshold voltages in both types of transistor.
Self-aligned twin well process: (a) an n-well formation using P donor implant and a photoresist mask; (b) p-well formation using B acceptor implant. A thick (~200 nm) "tank" oxide layer is grown wherever the silicon nitride-oxide stack is etched off, and the tank oxide is used to block the B implant in the n-wells in a self-aligned manner; (c) an isolation pattern for field transistors showing a B channel stop implant using a photoresist mask; (d) local oxidation of silicon wherever the nitride mask is removed, leading to thick LOCOS field oxide.
We can illustrate most of the common fabrication steps for MOS integrated circuits by studying the flow of a twin-well Self-Aligned SILICIDE (SALICIDE) CMOS process. This process is particularly important because most high-performance digital ICs, including microprocessors, memories and
application-specific ICs (ASICs) are made basically in this way. In order to make enhancement-mode n-channel devices, we need a p-type substrate, and vice versa. Since CMOS requires both, we must start either with an n-type or a p-type wafer and then make selected regions of the substrate have opposite doping by forming wells. For example, FIG. 5a shows a lightly doped p-epitaxial layer on a p+ -substrate. We can make n-channel devices in this layer. By implanting n-wells wherever needed, we can make p-channel devices also. This is an n-well CMOS process. Alternatively, if we start with an n-substrate and make p-wells in certain regions, we have a p-well CMOS process. For optimal device performance, however, it is usually desirable to separately implant both the n-and the p-well regions, which is called twin-well CMOS. The rationale for this can be appreciated if we keep in mind that for a state-of-the-art IC, typical doping levels are ~10^18 cm^-3 and junction depths are ~1 um in these wells. The doping levels have to be high enough to prevent punch-through breakdown due to drain-induced barrier lowering (DIBL) in the MOSFETs, but low enough to keep the threshold voltages acceptably small. If we choose to use the p-substrate for n-channel devices as in FIG. 5a, the p-type epitaxial layer must be doped to 1018 cm-3 , and the implanted n-type layer must be achieved by counter-doping at a level of ~2 * 10^18 cm^-3 , resulting in a net n-type doping of ~1 * 10^18 cm^-3 , but a total doping in this region of ~3 * 10^18 cm^-3. Such high levels of total doping are detrimental to carrier transport because they cause excessive ionized impurity scattering. Hence, for high performance ICs, the starting epitaxial doping level is generally very low (~10^16 cm^-3 ). This layer is grown on a heavily doped substrate (~10^19 cm^-3), to provide a highly conducting electrical ground plane. This helps with noise problems in ICs and helps minimize the problem of latchup by bypassing majority carriers (in this case holes) to the p+ substrate.
To form the twin wells in a self-aligned fashion, we first grow thermally a "pad" oxide (~20 nm) on the Si substrate, followed by low-pressure chemical vapor deposition (LPCVD) of silicon nitride (~20 nm). As shown in FIG. 5a, this oxide-nitride stack is covered by photoresist, and a window is opened for the n-well. Reactive ion etching (RIE) is then used to etch the oxide-nitride stack. Using the photoresist as an implant mask, we then do an n-type implant using phosphorus. Phosphorus is preferred to As for this purpose because P is lighter and has a higher projected range; also, P diffuses faster. This fast diffusion is needed to drive the dopants fairly deep into the substrate to form the n-well. After the implant, the photoresist is removed, and the patterned wafer is subjected to wet oxidation to grow a "tank" oxide (~200 nm). Note in FIG. 5b that the tank oxidation process consumes Si from the substrate, and the resulting oxide swells up. In fact, for every micron of thermally grown oxide, the oxidation consumes 0.44 um of Si, resulting in a 2. 2-fold volume expansion. The oxide does not grow in the regions that are protected by silicon nitride, because nitride blocks the diffusion of oxygen and water molecules (and thereby prevents oxidation of the Si substrate). The pad oxide that is used under the nitride has two roles: It minimizes the thermal-expansion mismatch and concomitant stress between silicon nitride and the substrate; it also prevents chemical bonding of the silicon nitride to the silicon substrate.
Using the tank oxide as a self-aligned implant mask (i.e., without actually having to do a separate photolithographic step), one does a p-type well implant using boron (B; FIG. 5b). The tank oxide must thus be much thicker than the projected range of the B. The concept of self-alignment is very important and is a recurring theme in IC processing. It is simpler and cheaper to use self-alignment than a separate lithographic step. It also allows a tighter packing density of the twin wells, because it is not required to account for lithographic misalignment during layout. The P and the B are then diffused into the substrate to a well depth of typically a micron by a drive-in diffusion at very high temperatures (~1000°C) for several hours. After this diffusion, the silicon nitride-oxide stack and the tank oxide are etched away. Since the tank oxidation consumes Si from the substrate, etching it off leads to a step in the Si substrate delineating the n-well and p-well regions. The step is important in terms of the alignment of subsequent reticles and is shown in an exaggerated fashion in FIG. 5c. The step, however, is disadvantageous from the depth-of-focus point of view during lithography. So, instead of a self-aligned twin-well process as just described, one often uses two separate lithography steps for the two well implants. This approach leads to a more planar structure, but a slightly larger well geometry because the wells are not self-aligned. There are many other variations of CMOS processes used, depending on the application.
Next, we form the isolation regions or the field transistors that guarantee that there will be no electrical cross talk between adjacent transistors, unless they are intentionally interconnected (FIG. 5c). This is achieved by ensuring that the threshold voltage of any parasitic transistor that may form in the isolation regions is much higher than the power supply voltage on the chip, so that the parasitic channel can never turn on under operating conditions. From the threshold voltage expression, we notice that VT can be raised by increasing substrate doping and increasing gate oxide thickness. However, a problem with that approach is the sub-threshold slope S , which degrades with increasing substrate doping and gate oxide thickness. One needs to optimize both VT and S such that the off-state leakage current in the field between transistors is sufficiently low at zero gate bias.
A stack of silicon dioxide-silicon nitride is photo-lithographically patterned as in FIG. 5c and subjected to RIE. A boron "channel stop" implant between the twin wells increases the acceptor doping and thus increases the threshold voltage in the p-well between the n-channel transistors (the field threshold). However, B will compensate the donor doping on the n-well side, and thus reduce the threshold in the n-well between p-channel devices. The B channel stop dose must thus be optimized to have acceptably high field thresholds in both types of wells.
After the channel stop implant, the photoresist is removed and the wafer with the patterned nitride-oxide stack shown in FIG. 5c (without photoresist) is subjected to wet oxidation to selectively grow a field oxide ~300 nm thick. The nitride layer blocks oxidation of the Si substrate in the regions where we plan to make the transistors. This procedure, where Si is oxidized to form SiO2 in regions not protected by nitride, is called LOCal Oxidation of Silicon (LOCOS). In this case, LOCOS provides electrical isolation between the two transistors, as shown in FIG. 5d.
The volume expansion of 2.2 * upon oxidation is an important issue because the selective oxidation occurs in narrow, confined regions. The compressive stress, if excessive, can cause dislocation defects in the substrate. Another issue is the lateral oxidation near the nitride mask edges, which causes the nitride mask to lift up near the edges, forming what is known as a bird's beak and causing a lateral moat encroachment of ~0.2 mm into each active region, thereby wasting precious Si real estate. There have been various modified LOCOS and other isolation schemes proposed to minimize this lateral encroachment. A notable example is Shallow Trench Isolation (STI) which involves using RIE to etch a shallow (~1 um) trench or groove in the Si substrate after the isolation pattern, filling it up completely by deposition of a dielectric layer of SiO2 and polysilicon by LPCVD, and then using chemical mechanical polishing (CMP) to planarize the structure (FIG. 6). This consumes less Si real estate compared with LOCOS, but gives superior isolation because the sharp corners at the bottom of the trench give rise to potential barriers that block leakage currents (the corner effect).
The pad oxide between the nitride and the Si surface minimizes the stress due to the nitride, and prevents bonding of the nitride to the Si, as mentioned above. Any residual nitride on the Si would retard subsequent gate oxide formation, leading to weak spots in the gate region of the MOSFETs. This problem is known as the white ribbon effect or the Kooi effect, after the Dutch scientist who first identified it. The pad oxide mitigates this problem, but does not solve it completely. Therefore, very often a "sacrificial" or "dummy" oxide is grown to consume a layer of Si containing any residual nitride, and this oxide is wet etched prior to the growth of the actual gate oxide.
In many modern CMOS processes, LOCOS has been supplanted by STI. Here, we use RIE to etch shallow grooves or trenches (~0.2 um deep) in the isolation regions. After growing a thin thermal oxide to passivate the surface, we fill up the trench with LPCVD oxide and grind the surface flat with CMP. STI has no moat encroachment, unlike LOCOS, and is capable of superior electrical isolation using less Si real estate.
Next, an ultra-thin (0.3 nm) gate oxide is grown on the substrate. Since the electrical quality of this oxide and its interface with the Si substrate is of paramount importance to the operation of the MOSFETs, dry oxidation is used for this step. This is followed by deposition of a high-k gate dielectric. It is immediately covered with LPCVD polysilicon or a metal gate electrode in order to minimize contamination of the gate oxide. The polysilicon gate layer is doped very heavily (typically n+ using a phosphorus dopant source, POCl3 in a diffusion furnace) all the way to the polysilicon-oxide interface in order to make it behave electrically like a metal electrode. Alternatively, the LPCVD polysilicon film may also be in situ doped during the deposition itself by flowing in an appropriate dopant gas such as phosphine or diborane. Heavy doping of the gate material is very important, because otherwise a depletion layer can be formed in the polysilicon gate (the poly depletion effect). This could result in a depletion capacitance in series with the gate oxide capacitance, thereby reducing the overall gate capacitance and, there fore, the drive current. The high doping (~10^20 cm^-3 ) in the polysilicon gate is also important for reducing the resistance of the gate and its RC time constant. The uniformly high doping in the polysilicon layer is facilitated by the presence of the grain boundary defects in the film, because diffusivity of dopants along grain boundaries is many orders of magnitude higher than in single-crystal Si. If metal gate electrodes such as TiN are used, these problems go away. Sometimes, a polysilicon gate may be deposited on a thin metal gate electrode to make a composite structure.
The doped polysilicon layer or metal gate is then patterned to form the gates, and etched anisotropically by RIE to achieve vertical sidewalls. That is extremely important because this etched gate is used as a self-aligned implant mask for the source/drain implants. As mentioned above, self-aligned processes are always desirable in terms of process simplicity and packing density. It is particularly useful in this case because we thereby guarantee that there will be some overlap of the gate with the source/drain but minimal overlap. The overlap is determined by the lateral scattering of the ions and by the lateral diffusion of the dopants during subsequent thermal processing (such as source/drain implant anneals). If there were no overlap, the channel would have to be turned on in this region by the gate fringing fields. The resulting potential barrier in the channel would degrade the device current. On the other hand, if there is too much overlap, it leads to an overlap capacitance between the source or drain and the gate. This is particularly bothersome near the drain end because it leads to the Miller overlap capacitance which causes undesired capacitive feedback between the output drain terminal and the input gate terminal.
Fabrication steps for the n-channel MOSFETs in the p-well are shown in FIG. 7 . After the polysilicon gate is etched, we first do a self-aligned n-type source-drain implant, during which the tank masking level is used to protect the PMOS devices with a layer of photoresist. The NMOS source and drain implants are done in two stages. The first implant is a lightly doped drain (LDD) implant (FIG. 7a). This is typically a dose of ~10^13 -10^14 cm^-2 , corresponding to a concentration of 10^18 -10^19 cm^-3 , and an ultra-shallow junction depth of 50-100 nm. When a MOSFET is operated in the saturation region, the drain-channel junction is reverse biased, resulting in a very high electric field in the pinch-off region. As we saw in Section 5.4 for reverse- biased p-n junctions, reducing the doping level increases the depletion width and makes the peak electric field at the junction smaller. As discussed, electrons traveling from the source to the drain in the channel can gain kinetic energy and thereby become hot electrons, which create dam age. The low doping in the LDD helps reduce hot carrier effects at the drain end. The shallow junction depths in the LDD are also important for reducing short channel effects such as DIBL and charge sharing. The penalty that we pay with the use of an LDD region is that the source-to-drain series resistance goes up, which degrades the drive current.
As the technology is evolving toward lower power supply voltages, hot carrier effects are becoming less important. This, along with the need to reduce series resistance, has driven the trend toward increasing doping in the LDD to levels above 10^19 cm^-3. In fact, the use of the term LDD then becomes a bit of a misnomer, and is often replaced by the term source/drain extension or tip.
After the LDD regions are formed alongside the polysilicon gate, we implant deeper (~200 nm) and more heavily doped (10^20 cm^-3 ) source and drain junctions farther away from the gate edges (FIG. 7d). This more conductive region allows ohmic contacts to the source and drain to be formed more easily than they could be directly to the LDD regions, and reduces the source/drain series resistance. This implant is done using a self-aligned scheme by the formation of sidewall oxide spacers. After removing the photoresist covering the PMOS devices, we deposit conformal LPCVD oxide (~100-200 nm thick) using an organic precursor called tetra-ethyl-ortho-silicate (TEOS) over the entire wafer at fairly high temperatures (~700°C) (FIG. 7b). The term conformal means that the deposited film has the same thickness everywhere, and follows the topography on the wafer. This oxide layer is then subjected to RIE, which is anisotropic (i.e., it etches predominantly in the vertical direction). If the RIE step is timed to just etch off the deposited oxide on the flat surfaces, it leaves oxide sidewall spacers on the edges of the polysilicon gate, as shown in FIG. 7c. This sidewall spacer is used as a self-aligned mask to protect the LDD regions very near the gate during the heavier, deeper n+ source and drain implants (FIG. 7d).
Next, the NMOS devices are masked by photoresist, and a p+ source and drain implant is done for the PMOSFETs (FIG. 8a). It may be noted that an LDD was not used for the PMOS. This is due to the fact that hot hole effects are less problematic than hot electron degradation, partly due to the lower hole mobility and partly due to the higher Si-SiO2 barrier in the valence band (5 eV) than in the conduction band (3.1 eV). After the source-drain implants are done, the dopants are activated and the ion implant damage is healed by a furnace anneal, or more frequently using a rapid thermal anneal. In this anneal we use the minimum acceptable temperature and time combination (the thermal budget) because it is critically important to keep the dopant profiles as compact as possible in ultra-small MOSFETs.
We can now appreciate why most CMOS logic devices are made on p-type substrates, rather than n-type. The n-channel MOSFETs generate a lot more substrate current due to hot carrier effects than PMOSFETs. The holes, thus generated, can more easily flow to ground in a p-type substrate, than in an n-substrate. Also, it is easier to dope substrates p-type with B during Czochralski crystal growth than n-type with Sb. Antimony is the preferred donor, rather than As or P for bulk doping of the Si melt, because Sb evaporates less than the other species.
The use of n+ polysilicon gates for both NMOS and PMOS devices raises some interesting device issues. Since the Fermi level in the n+ gate is very close to the Si conduction band, its work function is well suited to achieving a low VT for NMOS (Fms~ -1 V), but not for PMOS (Fms~0 V). From the VT expression, we notice that the second and third terms approach zero as thin-oxide technology evolves because Ci is getting larger. For high drive current we want VT to be in the neighborhood of ~0.3 to ~0.7 V for NMOS (-0.3 to -0.7 V for PMOS). We find from Eq. ( 6-38) that the p-well doping can be optimized to achieve the correct VT for the NMOS transistor, while at the same time being high enough to prevent punch-through breakdown between source and drain. For the PMOS transistor, on the other hand, an n-well doping of the order of 10^18 cm^-3 prevents punch-through, but the Fermi potential, hF, is so large and negative that the VT is too negative. That forces us to do a separate acceptor implant to adjust VT for the PMOS devices (FIG. 8b). The acceptor dose is low enough that the p-layer is fully depleted at zero gate bias, leading to enhancement-mode, rather than depletion-mode, transistors. In CMOS we try to make the negative VT of the PMOS device about the same value as the positive VT of the NMOS.
Close examination of the band diagram in the channel of the PMOSFET along the vertical direction (perpendicular to the gate oxide) shows that the energy minimum for the holes in the inversion layer is slightly below (~100 nm) the oxide-silicon interface, leading to what is known as buried channel operation for PMOS (FIG. 8c). On the other hand, for NMOS, the electron energy minimum in the inversion layer occurs right at the oxide-silicon interface, leading to surface channel operation.
1. There are good and bad aspects of this buried channel behavior for PMOS. Since the holes in the inversion layer of the PMOSFET travel slightly away from the oxide-silicon interface, they do not suffer as much channel mobility degradation as the electrons in the NMOSFET due to surface roughness scattering. That is good, because hole mobilities in Si are generally lower than electron mobilities, which forces us to make PMOS devices wider than the NMOSFETs to get similar drive currents. However, buried channel devices have a greater propensity toward DIBL and punch-through breakdown. Hence, as the size of MOSFETs is reduced, the DIBL problem becomes worse, and there is a desire to have surface channel operation for both NMOS and PMOS. Thus, there is interest in so-called dual gate CMOS, where n+ polysilicon gates are used for NMOSFETs and p+ gates are used for PMOSFETs. Such dual work function gates can be achieved by depositing the polysilicon undoped and then using the source and drain implants themselves to also dope the gates appropriately. This approach exploits the high polysilicon grain boundary diffusivities to degenerately dope the gates, at the same time having ultra-shallow source and drain junctions to minimize DIBL.
As a historical footnote, it may be added that MOSFETs initially used Al gates which could not withstand high temperature processing. Hence, the source and drain regions had to be formed first, either by diffusion or by implant, and then the Al gate was deposited and patterned. Such nonself-aligned processes suffered from the Miller capacitance mentioned previously. What made self-aligned source and drain regions viable was the use of polysilicon, which has a sufficiently high melting point to withstand subsequent processing. Recent research on MOSFET technology is going back full circle to metal gates, but this time using refractory metals such as tungsten (W). These metals have better conductivity than heavily doped polysilicon, and a work function that is better suited for CMOS. The Fermi level of W is near the middle of the Si band gap, which makes the flat band voltage and the threshold voltage more symmetric and better matched between NMOS and PMOS, and avoids the buried channel effect.
[1. We can qualitatively understand why the acceptor implant in the channel leads to such a buried channel behavior. Assume for a moment that the acceptor dose was high enough that the p-layer was not depleted at zero bias. In such a depletion-mode device, a positive gate bias to turn off the device would first deplete the surface region of holes, still leading to hole conduction deeper in the substrate away from the oxide-Si interface.]
The next step is to form a metal-silicon alloy or silicide in the source/drain and gate regions of the MOSFETs in order to reduce the series resistance (and thereby the RC time constants), and increase the drive current. This involves depositing a thin layer of a refractory metal such as Ti over the entire wafer by sputtering, and reacting the Ti with Si wherever they come in direct contact, by doing a two-step heat treatment in an N ambient (FIG. 9a). A 600°C anneal results in the formation of Ti2Si (the C49 phase according to metallurgists, which has fairly high resistivity), followed by an 800°C anneal which converts the Ti2Si to the C54 phase, TiSi2, which has an extremely low resistivity of ~17 u-Ohm-cm, much lower than that of the most heavily doped Si. On the other hand, the Ti on top of the sidewall oxide spacers does not form a silicide and stays as unreacted Ti or forms TiN because the process is done in an N ambient. The Ti and TiN can be etched off selectively by using a wet hydrogen peroxide-based etch, which does not attack the titanium disilicide, thereby electrically isolating the gates from the source/drains. Note that this process results in a SALICIDE without a separate masking level only on the source/drains and the polysilicon gate, where the silicide is often termed a polycide. This results in very high-performance MOSFETs.
Finally, the MOSFETs have to be properly interconnected according to the circuit layout, using the metallization level. This involves LPCVD of an oxide dielectric layer doped with B and P, which is known as boro-phospho-silicate glass (BPSG) on the entire wafer, patterning it by means of the contact-level reticle and using RIE to open up the contact holes to the substrate (FIG. 9b). The B and P allow the oxide layer to soften and reflow more readily upon annealing, thereby helping planarize or smooth out the topography on the wafer. This shaping of the millions of very small contact holes is critical on a ULSI chip, because otherwise metal deposited on the surface into the contact holes may not reach completely into the holes, leading to a catastrophic open circuit. In fact, sometimes a CVD tungsten layer is selectively deposited in the contact holes to form a contact plug before one proceeds to the next step. Then a suitable metal layer such as Al (alloyed with ~1 percent Si and ~4 percent Cu) is sputter deposited over the wafer, patterned using the metal interconnect level, and subjected to metal RIE. The Si is added to the Al to solve the junction spiking problem, whereby pure Al can incorporate the solid solubility limit of Si from the shallow source/drain regions. This would allow the Al to "spike," or short, through the p-n junction. The Cu is added to enlarge the grain size in the Al interconnect films, which are polycrystalline, making it harder for the electrons moving during current flow to nudge the Al atoms along, thereby opening voids (producing open circuits) in the interconnect. This is an example of an electromigration phenomenon. A cross-sectional picture of an LDD MOSFET with SALICIDE is shown in FIG. 9c.
In a modern ULSI chip, the complexity of the device layout generally demands that multiple levels of metallization be used for interconnecting the devices (FIG. 10). Hence, after the first metal is deposited, an intermetal dielectric isolation layer such as SiO2 is deposited by low-temperature CVD. Low temperatures are very important in this back-end part of the processing because by now all the active devices are in place and one cannot allow the dopants to diffuse significantly. Also, the metallization cannot withstand temperatures higher than ~500°C. The dielectric isolation layer must be suitably planarized prior to the deposition of the next layer of metal, and this is generally done by CMP. Planarization is important because if metal is deposited on a surface with rough topography and subjected to RIE, there can be residual metal sidewall filaments or "stringers" at the steps for the same reason one gets sidewall oxide spacers on either side of the MOSFET gate in FIG. 7 . These metal stringers can cause short circuits between adjacent metal lines. Planarization is also important in maintaining good depth of focus during photolithography. After planarization of the isolation layer, one uses photolithography to open up a new set of contact holes called vias, followed by deposition, patterning and RIE of the next layer of metal, and so on for multi-level metallization. As mentioned previously, W metal plugs are sometimes selectively deposited to fill up the via holes prior to the metal deposition, and reduce the likelihood of an open circuit.
Finally, a protective overcoat is deposited on the IC to prevent contamination and failure of the devices due to the ambient (FIG. 10). This generally involves plasma CVD of silicon nitride, which has the nice attribute that it blocks the diffusion of water vapor and Na through it. Sodium, as mentioned , causes a mobile ion problem in the gate dielectric of MOS devices. Sometimes, the protective overcoat is a BPSG layer. After the overcoat is deposited, openings are etched for the metal bond pads. After the chips are tested in an automated tester, the known good dies are packaged and wire bonded, as discussed in Section 6.
3.2 Integration of Other Circuit elements
One of the most revolutionary developments of integrated circuit technology is the fact that integrated transistors are cheaper to make than are more mundane elements such as resistors and capacitors. There are, however, numerous applications calling for diodes, resistors, capacitors, and inductors in integrated form. In this section we discuss briefly how these circuit elements can be implemented on the chip. We will also discuss a very important circuit element-the interconnection pattern that ties all of the integrated devices together in a working system.
Diodes. It is simple to build p-n junction diodes in a monolithic circuit. It is also common practice to use transistors to perform diode functions. Since many transistors are included in a monolithic circuit, no special diffusion step is required to fabricate the diode element. There are a number of ways in which a transistor can be connected as a diode. Perhaps the most common method is to use the emitter junction as the diode, with the collector and base shorted. This configuration is essentially the narrow base diode structure, which has high switching speed with little charge storage. Since all the transistors can be made simultaneously, the proper connections can be included in the metallization pattern to convert some of the transistors into diodes.
Resistors. Diffused or implanted resistors can be obtained in monolithic circuits by using the shallow junctions used in forming the transistor regions (FIG. 11a). For example, during the base implant, a resistor can be implanted which is made up of a thin p-type layer within one of the n-type islands. Alternatively a p region can be made during the base implant, and an n-type resistor channel can be included within the resulting p region during the emitter implant step. In either case, the resistance channel can be isolated from the rest of the circuit by proper biasing of the surrounding material. For example, if the resistor is a p-type channel obtained during the base implant, the surrounding n material can be connected to the most positive potential in the circuit to provide reverse-bias junction isolation. The resistance of the channel depends on its length, width, depth of the implant, and resistivity of the implanted material. Since the depth and resistivity are determined by the requirements of the base or emitter implant, the variable parameters are the length and width. Two typical resistor geometries are shown in FIG. 11b. In each case the resistor is long compared with its width, and a provision is made on each end for making contact to the metallization pattern.
Design of diffused resistors begins with a quantity called the sheet resistance of the diffused layer. If the average resistivity of a diffused region is t, the resistance of a given length L is R = tL/wt, where w is the width and t is the thickness of the layer. Now if we consider one square of the material, such that L = w, we have the sheet resistance Rs~t/t in units of ohms per square. We notice that Rs measured for a given layer is numerically the same for any size square. This quantity is simple to measure for a thin diffused layer by a four-point probe technique.
Therefore, for a given diffusion, the sheet resistance is generally known with good accuracy. The resistance then can be calculated from the known value of Rs and the ratio L/w (the aspect ratio) for the resistor. We can make the width w as small as possible within the requirements of heat dissipation and photolithographic limitations and then calculate the required length from w and Rs. Design criteria for diffused resistors include geometrical factors, such as the presence of high current density at the inside corner of a sharp turn. In some cases it is necessary to round corners slightly in a folded or zigzag resistor (FIG. 12b) to reduce this problem.
To reduce the amount of space used for resistors or to obtain larger resistance values, it is often necessary to obtain surface layers having larger sheet resistance than is available during the standard base or emitter implants. We can use a different implant, such as the VT adjust implant, to form shallow regions having very high sheet resistance (~ 10^5 ohm /square). This procedure can provide a considerable saving of space on the chip. In integrated FET circuits it is common to replace load resistors with depletion-mode transistors.
[2 This is a very useful method in which current is introduced into a wafer at one probe and is collected at another probe, and the voltage is measured by two probes in between. Special formulas are required to calculate resistivity or sheet resistance from these measurements.]
Capacitors. One of the most important elements of an integrated circuit is the capacitor. This is particularly true in the case of memory circuits, where charge is stored in a capacitor for each bit of information. FIG. 12 illustrates a one-transistor DRAM cell, in which the n-channel MOS transistor provides access to the adjacent MOS capacitor. The top plate of the capacitor is polysilicon, and the bottom plate is an inversion charge contacted by an n+ region of the transistor. The terms bit line and word line refer to the row and column organization of the memory (Section 5.2). One can also make use of the capacitance associated with p-n junctions.
Inductors. Inductors have not been incorporated into ICs in the past, because it is much harder to integrate inductors than the other circuit elements. Also, there has not been a great need for integrating inductors. Recently, that has changed because of the growing need for rf analog ICs for portable communication electronics. Inductors are very important for such applications, and can be made with reasonable Q factors using spiral wound thin metal films on an IC. Such spiral patterns can be defined by photolithography and etching techniques compatible with IC processing, or they can be incorporated in a hybrid IC.
Contacts and Interconnections. During the metallization step, the various regions of each circuit element are contacted and proper interconnection of the circuit elements is made. Aluminum is commonly used for the top metallization, since it adheres well to Si and to SiO2 if the temperature is raised briefly to about 550°C after deposition. Gold is used on GaAs devices, but the adhesion properties of Au to Si and SiO2 are poor. Gold also creates deep traps in Si.
As mentioned throughout this section, silicide contacts and doped polysilicon conductors are commonly used in integrated circuits. By opening windows through the oxide layers to these conductors, Al metallization can be used to contact them and connect them to other parts of the circuit. In cases where Al is used to contact the Si surface, it is usually necessary to use Al containing about 1% Si to prevent the metal from incorporating Si from the layer being contacted, thereby causing "spikes" in the surface. Thin diffusion barriers are also used between the Al and Si layers, to prevent migration between the two. The refractory silicides mentioned in Section 3.1 serve this purpose.
Increased complexity and packing density in integrated circuits inevitably leads to a need for multilayer metallization. Multiple levels of Cu metallization can be incorporated with interspersing dielectrics. In general, the metals may all be Al, Cu or they may be different conductors such as poly silicon or refractory metals (depending on the heat each is subjected to in subsequent processing). Also, the dielectrics may be deposited oxides, boro-phospho-silicate glass for reflow planarization, nitrides, and so on. The planarization of the surface is extremely important to prevent breaks in the metallization, which can occur in traversing a step on the surface. Various approaches using reflow glass, polyimide, and other materials to achieve planarization have been used, along with CMP.
The most important challenge in designing interconnects is the RC time constant, which affects the speed and active power dissipation of the chip. A very simplistic model of two layers of interconnects with an inter-metal dielectric (Figs. 13 and 14) shows that it can be regarded as a parallel plate capacitor. Regarding the interconnect as a rectangular resistor, its resistance is given by
where Rs is the sheet resistance, and the other symbols are defined in FIG. 14. The capacitance is given by
The RC time constant is then
Interestingly, for this simple one-dimensional model, the width of the interconnect w cancels out. Therefore, it does not make sense to use wider conductors for high-speed operation. It is also impractical to do so in terms of packing density. Of course, in reality we must account for the fringing electric fields, and therefore account for width dependence. From Eq. (eqn. 2), it is clear we need as thick a metal layer (within practical limits of deposition times and etching times) and as low a resistivity as possible. Low resistivities are also important in minimizing ohmic voltage drops in metal bus lines that carry power from one end of a chip to the other. Aluminum is very good in this regard, and thus was a mainstay for Si technology for many years. Aluminum also has other nice attributes such as good ohmic contacts to both n and p-type Si, and good adhesion to oxides.
Copper has even lower resistivity (1.7 u-Ohm-cm) than Al (3 u-Ohm-cm) and is about two orders of magnitude less susceptible to electromigration. Hence, it is an excellent alternative to Al for very high speed ICs (FIG. 13). The process breakthroughs that have made Cu viable for metallization include new electrodeposition and electroplating techniques because CVD or sputter deposition is not very practical for Cu. It is also very difficult to use RIE for Cu because the etch byproducts for Cu are not very volatile. Hence, instead of RIE, Cu patterning is based on the so-called Damascene process where grooves are first etched in a dielectric layer, Cu is deposited on it, and the metal layer is chemically-mechanically polished down, leaving inlaid metal lines in the oxide grooves. In this method, the metal does not have to be etched directly using RIE, which is always a difficult process. The name "damascene" is derived from a metallurgical technique in ancient Turkey where metal artwork was inlaid into swords and other artifacts using this type of process. Copper can create traps deep in the band gap of Si; hence, a suitable barrier layer such as Ti is needed between the Cu layer and the Si substrate.
Other parameters in Eq. (eqn. 2) that can minimize the RC time constant are clearly the use of a thick inter-metal dielectric layer (once again within the limits of practicality in terms of deposition times), and as low a dielectric constant material as possible. Silicon dioxide has a relative dielectric constant of 3.9. There is active research in low dielectric constant materials (sometimes referred to as low-k materials). These include organic materials such as polyimides, or xerogels/aerogels which have air pockets or porosity purposely built in to minimize the dielectric constant.
In designing the layout of elements for a monolithic circuit, topological problems must be solved to provide efficient interconnection without crossovers-points at which one conductor crosses another conductor. If crossovers must be made on the Si surface, they can be accomplished easily at a resistor. Since the implanted or diffused resistor is covered by SiO2, a conductor can be deposited crossing the insulated resistor. In cases requiring crossovers where no resistor is available, a low-value implanted resistor can be inserted in one of the conductor paths. For example, a short n+ region can be implanted during the source/drain step and contacted at each end by one of the conductors. The other conductor can then cross over the oxide layer above the n+ region. Usually, this can be accomplished without appreciable increase in resistance, since the n+ region is heavily doped and its length can be made small.
During the metallization step, appropriate points in the circuit are connected to relatively large pads to provide for external contacts. These metal pads are visible in photographs of monolithic circuits as rectangular areas spaced around the periphery of the device. In the mounting and packaging process, these pads are contacted by small Au or Al wires or by special techniques such as those discussed in Section 6.