<<PREV.
5. Ultra largescale Integration (ULSI)
In the early development of integrated circuits it was felt that the inevitable
defects that occur in processing would prevent the fabrication of devices
containing more than a few dozen logic gates. One approach to integration
on a larger scale tried in the late 1960s involved fabricating many identical
logic gates on a wafer, testing them, and interconnecting the good ones
(a process called discretionary wiring). While this approach was being developed,
how ever, radical improvements were made in device processing which increased
the yield of good chips on a wafer dramatically. By the early 1970s it was
possible to build circuits with many hundreds of components per chip, with
reasonable yield. These improvements made discretionary wiring obsolete
almost as soon as it was developed. By reducing the number of processing
defects, improving the packing density of components, and increasing the
wafer size, it is now possible to place millions of device elements on a
single chip of silicon and to obtain many perfect chips per wafer.
A major factor in the development of integrated circuits has been the continual
reduction in size of the individual elements (transistors, capacitors) within
each circuit. Through improved design and better lithography, there has
been a dramatic shrinking of the minimum feature size (e.g., a transistor
gate) used in these devices. The results of shrinking the elements in a
256MbDRAM are shown in FIG. 20. By reducing the minimum feature size
in successive steps from 0.13 to 0.11 um, the die area was reduced from
about 135 mm^{2} in the firstgeneration design to less than 42 mm^{2} in the
fifthgeneration device.
Obviously, more of the smaller chips can be made by batch fabrication on
the wafer, and the effort in shrinking the design is rewarded in a more
profitable device.
Successive designs using reduced feature sizes have made dramatically increased
circuit complexity possible. DRAM design has set the pace over the past
two decades, in which successive 1 Mb, 4Mb, and 16Mb memories led to
similar powers of two increase to the Gb range. FIG. 21 illustrates
the size comparison of a 128Mb memory with an equivalent amount of memory
in the form of two 64Mb and eight 16Mb chips. These are examples of ULSI.
Although the achievement of many powers of two in memory is impressive
and important, other ULSI chips are important for the integration of many
different system functions. A microprocessor includes functions for a computer
central processing unit (CPU), along with memory, control, timing, and interface
circuits required to perform very complex computing functions. The complexity
of such devices is shown in FIG. 22, which illustrates a microprocessor
chip.
Before leaving this section it might be useful to provide some calibration
regarding the dimensions we have been discussing. FIG. 23 com pares
the size of 64Mb DRAM circuit interconnect elements with a human hair,
on the same scale. We can see that the densely packed 0.18 mm lines on this
ULSI memory chip are dwarfed by the scanning electron micrograph of a human
hair which has the diameter of about 50 microns. Current generation DRAMs
have feature sizes of ~25 nm (0.025 mm).
Although the focus of this guide is devices and not circuits, it is important
to look at some typical applications of MOS capacitors and FETs in semiconductor
logic and memory ULSI, which constitute about 90, of all ICs. This should
give the reader a better feel for why we have studied the physics of MOS
devices in Section 6. This is clearly not a comprehensive discussion, because
the design and analysis of circuits is a large subject covered in other
books and courses. We will first look at some digital logic applications,
followed by some typical memory devices.
FIG. 22 An example of ULSI, the Intel 22nm quad core processor with
1.4 billion transistors. (Photograph courtesy of Intel.)
FIG. 23 Size comparison of ULSI circuit elements with human hair: (a)
densely packed 0.18mm interconnect lines in the array of a 64Mb DRAM
chip; (b) scanning electron micrograph of a human hair. Both micrographs
are shown to the same scale. (© 2004 Micron Technology, Inc. All rights
reserved. )
FIG. 24 Resistor load inverter voltage transfer characteristics (VTC):
(a) NMOSFET with load resistor RL and load parasitic capacitance C; (b)
determination of VTC by superimposing the load line (linear IV ohmic characteristics
of the resistor) on NMOSFET output characteristics; (c) VTC showing output
voltage as a function of input voltage. The five key points on the VTC are
logic high (VOH), logic low (VOL), unity gain points (VIL and VIH), and
logic threshold where input equals output (Vm).
5.1 Logic devices
A very simple and basic circuit element is the inverter, which serves to
flip the logic state. When its input voltage is high (corresponding to logic "1"),
its output voltage is low (logic "0"), and vice versa. Let us
start the analysis with a resistorloaded nchannel MOSFET inverter to illustrate
the principles in the simplest possible manner (FIG. 24a). Then, we will
extend the treatment to the slightly more complicated CMOS inverters which
are much more useful and more common today.
A key concept for inverters is the voltage transfer characteristic (VTC),
which is a plot of the output voltage as a function of the input bias (FIG. 24c). The VTC gives us information, for example, about how much noise
the digital circuit can handle, and the speed of switching of the logic
gates. There are five key operating points (marked I through V) on the VTC.
They include VOH, corresponding to the logic high or "1", VOL,
corresponding to the logic low or "0", and Vm, corresponding to
the intersection of a line with unity slope (where Vout = Vin) with the
VTC. Vm, known as the logic threshold (not to be confused with the VT of
the MOSFETs), is important when two inverters are crosscoupled in a flipflop
circuit because the output of one is fed to the input of the other, and
vice versa. Two other key points are the unity gain points, VIL and VIH.
The significance of these points is that if the input voltage is between
them, the change of the input is amplified and we get a larger change of
the output voltage. Outside of this operating range, the change of the input
voltage is attenuated. Clearly, any noise voltage which puts the input voltage
between VIL and VIH would be amplified, and lead to a potential problem
with the circuit operation.
Let us see how to go about determining the VTC. From the circuit in FIG. 24a,
we see that in the output loop from the power supply to ground, the current
through the resistor load is the same as the drain cur rent of the MOSFET.
The power supply voltage is equal to the voltage drop across the resistor
plus the draintosource voltage. To determine the VTC, we superimpose
the load line of the load element (in this case a straight line for an ohmic
resistor) on the output characteristics of the MOSFET (FIG. 24b). This
is similar to our load line discussion. The load line goes
through VDD on the voltage axis because when the current in the output
loop is zero, there is no voltage drop across the resistor and all the
voltage appears across the MOSFET. On the current axis, the load line goes
through VDD/RL because when the voltage across the MOSFET is zero, the
voltage across the resistor must be VDD. As we change the input bias, Vin,
we change the gate bias on the MOSFET, and thus in FIG. 24b, we go from
one constant VG curve to the next. At each input bias (and a corresponding
constant VG curve) the intersection of the load line with that curve tells
us what the drain bias VD is, which is the same as the output voltage. This
is because at the point of intersection, we satisfy the condition that for
the dc case where the capacitor does not play any role, the current through
the resistor is the same as the MOSFET current. (Later on, we shall see
that in the ac case when the logic gates are switched, we need to worry
about the displacement current through the capacitor when it is charged
or discharged.) It can be clearly seen from FIG. 24c that as the input
voltage (or VG) changes from low to high, the output voltage decreases from
a high of VDD to a low of VOL. We can solve for any point on this VTC curve
analytically simply by recognizing whether the MOSFET is in the linear region
or in saturation, using the corresponding drain current expression [Eq.
( 649) or ( 653)] and setting it equal to the resistor current. As an
illustration, suppose we want to determine the logic "0" level,
VOL. This occurs when the input VG is high and the output VD is low, putting
the transistor in the linear region. Using Eq. ( 649), we can write
(eqn. 3a)
Since in the dc case the current through the MOSFET is the same as that
through the resistor,
(eqn. 3b)
We can solve for VOL if we know RL and the MOSFET parameters. Alternatively,
we can design the value of RL to achieve a certain VOL. What might dictate
the choice of RL? We shall see later in this section that for many applications
we use two of these inverters in a crosscoupled manner to form a bistable
flipflop. The output of one inverter is fed back to the input of the other,
and vice versa. Clearly, the VOL must be designed to be significantly less
than the VT of the MOSFET. Otherwise, neither MOSFET will be fully turned
off, and the flipflop will not function properly. Similarly, all the other
points on the VTC can be determined analytically by using the appropriate
MOSFET drain current expression, and setting it equal to the current through
the resistor.
We can make some general observations from this analysis. We want the transition
region of the VTC (between VIL and VIH) to be as steep (i.e., high gain)
as possible, and the transition should be around VDD/2. High gain guarantees
a highspeed transition from one logic state to the other. It is necessary
to increase the load resistance to increase this gain in the transition
region.
The transition around VDD/2 guarantees high noise immunity or mar gin for
both logic "1" and logic "0" levels. To appreciate the
importance of noise immunity, we must recognize that in combinatorial or
sequential digital circuits, the output of one inverter or logic gate is
often fed into the input of the next stage. Noise immunity is a measure
of how much noise voltage the circuit can tolerate at the input, and still
have the digital outputs be at the correct logic level in the subsequent
stages. For example in FIG. 24c, if the input is nominally at zero, the
output should be high (logic "1"). If this is fed into another
inverter stage, its output should be low, and so on. If a noise spike causes
the input of the first stage to go above Vm, the output volt age decreases
sufficiently to potentially create errors in the digital levels in subsequent
stages. Having a symmetric transition of the VTC around VDD/2 ensures that
the noise margin is high for both logic levels.
One problem with the resistor load inverter is that the VOL is low, but
not zero. This, coupled with the fact that the load element is a passive
resistor that cannot be turned off, causes high standby power dissipation
in this circuit. These problems are addressed by the CMOS structure described
next.
We can determine the VTC for the CMOS case exactly as for the resistor
load, although the math is somewhat more messy (FIG. 25). As mentioned
previously, for an input voltage Vin, the VG of the NMOSFET is Vin, but
that of the PMOSFET is Vin VDD. Similarly, if the output voltage is Vout,
the VD of the NMOSFET is Vout, but that of the PMOS is Vout VDD. The load
element now is not a simple resistor with a linear currentvoltage relationship,
but instead is the PMOSFET device whose "load line" is a set of
ID VD output characteristics (FIG. 25b). The Vout can be determined as
a function of the Vin by recognizing whether the NMOSFET and the PMOSFET
are in the linear or saturation region of their characteristics, and using
the appropriate current expressions. At each point, we would set the NMOSFET
ID equal to the PMOSFET ID.
FIG. 25 CMOS inverter voltage transfer characteristics: (a) NMOSFET
with PMOSFET load and load parasitic capacitance, C; (b) determination of
VTC by superimposing load line (output characteristics of PMOSFET shown
as dotted line) on NMOSFET output characteristics; (c) VTC showing output
voltage as a function of input voltage. The five key points on the VTC are
logic high (VOH), logic low (VOL), unity gain points (VIL and VIH), and
logic threshold where input equals output (Vm); (d) switching current from
VDD to ground when the input voltage is in a range where both the NMOSFET
and the PMOSFET are on.
As in the case of the resistive load, there are five key points on the
VTC (FIG. 25c). They are logic "1" equal to VDD, logic "0" equal
to 0, logic threshold Vm where Vin = Vout, and the two unity gain points,
VIH and VIL. In region I in FIG. 25c, the NMOSFET is OFF, and Vout = VDD.
Similarly, in region V, the PMOSFET is OFF, and Vout = 0. We can illustrate
the calculation in region II, where the NMOSFET is in saturation and the
PMOSFET is in the linear region. In this case, we must use Eq. ( 653) for
the saturation drain current of the NMOSFET. We are considering the long
channel case.
(eqn. 4a)
On the other hand, we must use Eq. ( 649) for the PMOSFET in the linear
region.
(eqn. 4b)
Here VTN and VTP are the nand pchannel threshold voltages. In the dc
case, since the output load capacitor does not play a role, the drain current
through the PMOSFET device must be equal in magnitude to that through the
NMOSFET. (However, for the ac case, we need to consider the displace ment
current through the capacitor.)
IDN = IDP (eqn. 5a)
Using Eq. ( 653) for the NMOSFET in saturation, and Eq. ( 649) for the
PMOSFET in the linear region.
(eqn. 5b)
From Eq. (eqn. 5b), we can get an analytical relation between the input and
output voltages valid in region II. We can get similar relationships in
the other regions of the VTC.
Region IV is very similar to region II in FIG. 25c, except that now the
NMOS is in the linear regime, while the PMOSFET is in saturation. In region
III, both the NMOSFET and the PMOSFET are in saturation. Since the output
impedance of a MOSFET is very high, this is tantamount to a semiinfinite
load resistor, thereby resulting in a very steep transition region. That
is why a CMOS inverter switches faster than the resistor load case. The
CMOS inverter is also preferable because in either logic state (regions
I or V), either the NMOSFET or the PMOSFET is OFF, and the standby power
dissipation is very low. In fact, the current in either logic state corresponds
to the (very low) source/drain diode leakage.
We want the transition region (region III) to be at VDD/2 from the point
of view of symmetry and noise immunity. Once again, by setting the NMOSFET
ID equal to that of the PMOSFET, it can be shown that the transition occurs
at
(eqn. 6a) where
(eqn. 6b)
We can design Vin to be at VDD/2 by choosing VTN = VTP and x = 1. Since
the effective electron mobility in the channel of a Si MOSFET is roughly
twice that of the hole mobility, we must design CMOS circuits to have a
(Z/L)P = 2(Z/L)N to achieve the condition x = 1.
We can combine such CMOS inverters to form other logic gates for combinatorial
circuits such as NOR gates and NAND gates (FIG. 26). The truth tables
for these gates are shown in FIG. 27 . By applying combinations of logic "high" or
logic "low" to inputs A and B, we get the output states cor responding
to the truth tables. The synthesis of logic circuits corresponding to these
truth tables can be done using Boolean algebra and De Morgan's laws. The
upshot of these laws is that any logic circuit can be made using inverters
in conjunction with either NAND gates or NOR gates. Which would be preferable
from a device physics point of view? We see from FIG. 26, that in the
NOR gate the PMOSFET devices T3 and T4 are in series, while for the NAND
it is the NMOSFETs (T1 and T2). Since the electron channel mobilities are
twice hole mobilities, we would obviously prefer NMOSFETs. Therefore, the
preferred choice is NAND, along with inverters.
FIG. 26 Logic gates and CMOS implementation of (a) NOR gate (b) NAND
gate.
We can also estimate the power dissipation in the inverter circuit. We
already know that the standby power dissipation is very small, being governed
by the OFF state leakage current of either the NMOSFET or the PMOSFET,
depending on the logic state. This leakage current depends on the source
and drain diode leakage currents, or if the VT is low, on the subthreshold
leakage of the MOSFET that is turned OFF.
While the inverter is switching, there is also a transient current from
the power supply to ground when both the transistors are ON (see FIG. 25d).
This is known as the switching current or the commutator current. The magnitude
of this current will clearly depend on the values of VTN and VTP. The higher
the magnitudes of the thresholds, the less is the input voltage swing for
which both the PMOSFET and the NMOSFET will be ON while the input voltage
is being changed. The commutator current is then less during switching,
which is desirable from a reduced power dissipation point of view. However,
this reduction of power dissipation by increasing threshold voltages is
obtained at the expense of reduced drive current and, therefore, overall
speed of the circuit.
FIG. 27 (a) AND/NAND logic symbols and truth table; (b) OR/NOR logic
symbols and truth table; (c) XOR logic symbol and truth table.
The speed penalty due to reduction of drive current is because in a digital
circuit, while switching between logic states, the MOSFET drive currents
must charge and discharge the parasitic capacitors that are inevitably associated
with the output node (FIG. 25a). There is also some power dissipation
involved in charging and discharging load capacitors attached to the output
of the inverter. This load capacitance depends mostly on the input gate
oxide capacitance of the MOSFETs of the next inverter stage (or logic gate)
that this inverter (or logic gate) may be driving, along with some small
parasitic capacitances. The input load capacitance of a single inverter
is given by gate oxide capacitance per unit area Ci times the device areas.
(eqn. 7)
The total load capacitance is then multiplied by a factor that depends
on the fanout of the circuit, which is the number of gates that are being
driven in parallel by the inverter (or logic gate). It is necessary to add
up the load capacitances for all the inverters or logic gates that are being
driven by this inverter stage. The energy expended in charging up the equivalent
load capacitor, C, is the integral of the product of the timedependent
voltage times the timedependent displacement current through the capacitor
during the charging cycle.
(eqn. 8a)
The energy stored in C is then obtained by considering the displacement
current (ip(t) = C dv/dt) through the capacitor:
(eqn. 8b)
Similarly, during one discharging cycle we get
(eqn. 9)
If the inverter (or gate) is being charged and discharged at a frequency
f, we get an active power dissipation
(eqn. 10)
In addition to power dissipation, we are also concerned with the speed
of logic circuits. The speed of a gate, such as the one shown in FIG. 25,
is determined by the propagation delay time tP. We define the time required
for the output to go from the logic high VOH to VOH/2 as tPHL. The converse
(to go from logic low VOL(= 0) to VOH/2) is defined as tPLH. We can write
down approximate estimates for these times by recognizing that for the output
to go from high to low (or logic "1" to "0"), the NMOSFET
has to discharge the output node toward ground. During this period, the
NMOSFET will be in saturation. Assuming a constant saturation current as
an approximation, we obtain
(eqn. 11a)
This is the decrease of charge on the capacitor divided by the discharging
current. Conversely,
(eqn. 11b)
Knowing these times helps us considerably in designing circuits
that meet the speed requirements of a design. Of course, for accurate
numerical estimates of these propagation time delays or of the power dissipation
we need to use computers. A very popular program to do so is the Simulation
Program with Integrated Circuit Emphasis (SPICE). This discussion illustrates
that the device physics plays an important role in the design and analysis
of such circuits.
5.2 Semiconductor Memories
In addition to logic devices such as microprocessors, integrated circuits
depend on semiconductor memories. We can illustrate many key MOS device
physics issues by looking at three of the most important types of semiconductor
memory cells: the static randomaccess memory (SRAM), the dynamic randomaccess
memory (DRAM), and the nonvolatile flash memory cell. SRAMs and DRAMs are
volatile in the sense that the information is lost if the power supply is
removed. For flash memories, however, information is stored indefinitely.
For SRAMs, the information is static, meaning that as long as the power
supply is on, the information is retained. On the other hand, the information
stored in the cells of a DRAM must periodically be refreshed because stored
charge representing one of the logic states leaks away rapidly. The refresh
time must be short compared with the time needed for stored charge to degrade.
FIG. 28 Organization of a random access memory (RAM): The memory array
consists of memory cells arranged in an orthogonal array. There is one memory
cell at the intersection of one row (wordline) and one column (bitline).
To address a particular memory cell, the N row addresses are latched in
from the N address pins, and decoded by the 2N row decoders. All the memory
cells on the selected row are read by the 2N sense amplifiers. Of those,
a cell (one bit) or group of cells (byte or word) is selected for transfer
to the data output buffers depending on the column addresses that are decoded
by the 2N column decoders. Generally, to save pin count on the package,
the N column addresses are provided in a multiplexed fashion to the same
N address pins as the row addresses, after the row addresses have already
been latched in.
The overall organization of all these types of memories is rather similar,
and is shown in FIG. 28. We will not describe the memory organization
in great detail here, but will instead focus on the device physics. We need
to know the type of cell that is used at the intersection of the rows or
word lines, and the columns or bitlines. These memories are all random access
in the sense that the cells can be addressed for write or read operations
in any order, depending on the row and column addresses provided to the
address pins, unlike memories such as hard disks or floppy disks on a computer
which can only be addressed sequentially. Generally, the same set of pins
is used for both the row and the column addresses, in order to save pin
count. This forces us to use what is known as address multiplexing. First,
the row addresses are provided at the address pin, and decoded using row
decoders. For N row addresses, we can have 2N rows or wordlines. The row
decoders then cause the selected wordline to go high, so that all the 2N
cells (corresponding to N column addresses) on this wordline are accessed
for either read or write, through sense amplifiers at the end of the 2N
columns or bitlines. After the appropriate row has been decoded, the appropriate
column addresses are provided to the same address pins, and the column decoders
are used to select the bit or group of bits (known as byte or word) out
of all the 2N bits on the selected wordline. We can either write into or
read from the selected bit (or group of bits) using the sense amplifiers,
which are basically flipflops or differential amplifiers.
FIG. 29 An array of 4 CMOS SRAM cells. The bitline and bitline ( bitlinebar)
are logical complements of each other.
SRAMs. A group of four 6transistor CMOS SRAM cells is shown in FIG. 29.
Each cell is found in this case at the intersection of a row or wordline,
and a column or bitline (along with its logical complement known as bitlinebar).
The cell is a flipflop, consisting of two crosscoupled CMOS inverters.
Clearly, it is bistable: if the output of one inverter is high (corresponding
to the NMOSFET being OFF, and the PMOSFET ON), that high voltage is fed
to the input of the other crosscoupled inverter, and the output of the
other inverter will be low. This is one logic state (say "1")
of the SRAM. Conversely, the other stable state of the flipflop can be
considered to be the other logic state (say "0"). Many of the
device issues are identical to those described earlier in connection
with the VTC of inverters. We aim for a symmetric transition from VOH to
VOL at VDD/2 with a high gain in the transition region, to improve noise
immunity and speed of convergence of the SRAM cell. The speed of convergence
determines how fast the SRAM flipflop latches into one stable logic state
or the other. The cells are accessed through two access transistors whose
gates are controlled by the wordline. That is why this is called a 6transistor
cell. Other SRAM cells use load resistors in the inverters, rather than
PMOSFETs, leading to a 4transistor, 2resistor cell. As discussed, the
CMOS cell has superior performance, but at the expense of occupying more
area.
Unless the row decoders cause a particular wordline to go high, the SRAM
cells on that wordline are electrically isolated. By selecting a particular
wordline, the access transistors on that row are turned ON and act as logic
transmission gates between the output nodes of the SRAM cell and the bitline
and its complement, the bitlinebar. During a read operation, the bitline
and its complement are both precharged to the same voltage. Once the access
transistors are turned ON, a small voltage differential develops between
bitline and bitlinebar because the output nodes of the SRAM are at different
voltages (0 and VDD). The voltage differential that is established is due
to a charge redistribution that occurs between the parasitic capacitance
associated with the output nodes of the SRAM and the bitline capacitance.
This voltage difference is amplified by the sense amplifiers. As mentioned
previously, the sense amplifiers are differential amplifiers, very similar
in configuration to the SRAM flipflop cell itself. The bitline and bitlinebar
(complement of the bitline) are fed to the two inputs of the sense amplifier,
and the voltage differential is amplified until the voltage separation is
VDD.
FIG. 30 One transistor, one capacitor DRAM cell equivalent circuit:
the storage MOS capacitor is connected to the bitline through the pass
transistor (MOSFET switch) whose gate is controlled by the wordline.
DRAMs. The DRAM cell structure is shown in FIG. 30. The information is
stored as charge on an MOS capacitor, which is connected to the bitline
through a switch which is an MOS pass transistor, the gate of which is controlled
by the wordline. There is one such cell at each intersection of the orthogonal
array of wordlines and bitlines, exactly as for SRAMs. When the wordline
voltage becomes higher than the VT of the pass transistor (MOSFET between
the bitline and the storage capacitor), the channel is turned ON, and connects
the bitline to the MOS storage capacitor. The gate of this capacitor (or
capacitor plate) is permanently connected to the power supply voltage VDD,
thereby creating a potential well under it which tends to be full of inversion
electrons for a ptype substrate (FIG. 31a). We apply either 0 V to the
bitline (generally corresponding to logic "0"), or VDD (corresponding
to logic "1"), and the appropriate voltage appears as the substrate
potential of the MOS capacitor. For a stored "0" in the cell,
the potential well that is created under the MOS capacitor by the plate
voltage is full of inversion charge (FIG. 31b,c). When the wordline voltage
is turned low such that the MOS pass transistor is turned off, the inversion
charge under the storage capacitor stays the same; this is the stable state
of the capacitor. On the other hand, if a positive voltage (VDD) is applied
to the bitline, it draws out the inversion electrons through the pass transistor
(FIG. 31d,e). When the pass transistor is cut off, we end up with an empty
potential well under the MOS capacitor plate. Over a period of time, the
potential well tends to be filled up by minority carrier electrons that
are constantly created by thermal generationrecombination in the substrate
and are collected under the charged MOS capacitor plate. Hence, the logic "1" degrades
towards the logic "0". That is why a DRAM is considered to be "dynamic" unlike
an SRAM. It is necessary to periodically restore the logic levels or "refresh" the
stored information.
FIG. 31 DRAM cell structure and cell operation: (a) cell structure
corresponding to equivalent circuit of FIG. 30; (b)(e) potentials under
bitline, pass transistor channel and storage capacitor during write "0",
store "0", write "1" and store "1" operations.
It shows that the logic state "0" corresponds to a filled potential
well (stable state), while the logic state "1" corresponds to
an empty potential well (unstable state) that is filled up over time by
minority carriers generated in the substrate and leakage through the pass
transistor.
There are interesting device physics issues regarding the pass transistor.
This is like the access transistor in the SRAM, or a logic transmission
gate. We see that in this MOSFET, neither the source nor the drain is permanently
grounded. In fact, which side acts as the source and which as the drain
depends on the circuit operation. When we are writing a logic "1" into
the cell, the bitline voltage is held high (=VDD). As this voltage is writ
ten into the cell, it is as if the source of the pass transistor gets charged
up to VDD. Another way of looking at this is that with respect to the source,
the substrate bias of the pass transistor is VDD. The body effect of the
MOSFET causes its VT to increase. This is very important
because for the pass transistor to operate as a transmission gate it is
necessary that it be in the linear regime throughout, and not get into
saturation (with a concomitant voltage drop across the pinchoff region).
Hence, the gate or the wordline voltage must be held at VDD (which is the
final voltage of the source/drains) plus the VT of the MOSFET, taking body
effect into account. It is also important to make sure that the leakage
of the pass transistor is low enough to satisfy refresh requirements of
the DRAM. Not only must the source/drain diodes be low leakage, but the
VT and the subthreshold slope must be optimized such that subthreshold
leakage for the grounded wordline case is low enough.
FIG. 32
CV characteristics of DRAM MOS capacitor in stored "0" and stored "1" states.
The difference of area under the CV curves shown by hatchmarked pattern
reflects the charge differential between the two states.
The stored charge difference between the two logic states can be deter
mined by looking at the capacitancevoltage ( CV) characteristics of the
MOS capacitor (FIG. 32). For a stored "1", essentially there
is a substrate bias applied to the MOS capacitor, which raises its VT due
to the body effect. Hence, the CV characteristics shift
to the right for a stored "1". Since the MOS capacitance is not
a fixed capacitance, but is voltage dependent, we saw earlier that it must
be defined in a differential form. Alternatively, we can write down the
stored charge under the capacitor as
(eqn. 12)
FIG. 33 Equivalent circuit showing charge redistribution between cell
capacitance (CC) and bitline capacitance (C ) on one side, versus dummy
cell (C ) and bitline capacitance (C ) on other.
This is simply the area under the CV curve. The charge differential that
distinguishes the logic "1" and the logic "0" is the
difference of areas under the capacitancevoltage curves in the two cases
(FIG. 32).
When reading the cell, the pass transistor is turned on, and the MOS storage
capacitor charge is dumped on the bitline capacitance CB, precharged to
VB (typically = VDD). The swing of the bitline voltage will clearly depend
on the voltage VC stored in the storage cell capacitance CC. As in the case
of the SRAM, the change of the bitline voltage depends on the capacitance
ratio between the bitline and the cell. To do differential sensing in the
case of DRAMs, we do not use two bitlines per cell as for SRAMs. Instead,
we compare the bitline voltage for the selected cell with a reference bitline
voltage to which is connected a dummy cell whose MOS capacitance, CD, is
roughly half that of the actual cell capacitance, CC. Typical values of
CB, CC, and CD in a DRAM are 800 fF, 50 fF, and 20 fF, respectively. The
voltage differential that is applied to the sense amplifier then becomes
(FIG. 33)
(eqn. 13a)
If VD is set to zero, the expression simplifies to:
(eqn. 13b)
Putting the cell voltage VC equal to 0 V or 5 V, and typical, acceptable
bitlinetocell capacitance ratios CB/CC(= 1520) in Eq. (eqn. 13b), we
get different polarities of the differential voltage of the order of {100
mV for logic "1" and
logic "0", respectively, which can be detected by sense amplifiers.
From Eq. (eqn. 13b), it can be seen that for much higher bitlinetocell
capacitance ratios, the swing of the bitline voltage will be negligible,
regardless of the cell voltage. The minimum required cell capacitance CC
is about 50 fF, governed by socalled soft errors. DRAMs, like everything
else on Earth, are constantly being bombarded by cosmic rays, and highenergy
alpha particles can create electronhole pairs in semiconductors. A typical
collected charge due to one of these events is about 100 fC. This spurious
charge can be neglected if the cell capacitance is 50 fF and 5 V is applied
to the cell, for which the stored charge is roughly 250 fC. The DRAM cell
then becomes immune to typical alpha particle hits.
FIG. 34 Various approaches (past, present, and future) of achieving
higher DRAM cell capacitance and charge storage density without increasing
cell size. As = Area on wafer taken by capacitor; Ac = Area of capacitor.
For a planar capacitor Ac = As; however, for nonplanar structures Ac 7
As. C = Ac P/d is the capacitance; and Q = CV is the total stored charge
in a fixed, voltageindependent capacitor.
Maintaining a cell capacitance of 50 uF as the cell dimensions are reduced
from one generation of DRAM to the next is a tremendous technological challenge.
One way to look at this problem is shown in FIG. 34. The challenge is
to store more charge per unit area on the planar surface (As) of the Si
substrate. Approximating the MOS capacitance as a fixed, voltageindependent
capacitor, we can write the stored charge Q as
Q = CV = (PAC / d)V (eqn. 14)
where g is the permittivity of the dielectric, d is its thickness, and
AC is the capacitor area. As shown in FIG. 34, the historical way of achieving
the desired capacitance has been to scale the dielectric thickness, d. But
that runs into the problems discussed in Section 6.4.7. Another approach,
which is being taken currently, is to use fabrication schemes to increase
the area devoted to the MOS storage capacitor, Ac, even as we reduce the
planar surface area on the wafer, As, used for making this storage capacitance.
Obviously, this can be done by moving away from a purely planar structure,
and exploiting the third dimension. We can go down into the Si by digging "trenches" in
the substrate with RIE and forming a trench storage capacitor on the sidewalls
of the trench (FIG. 35a). Alternatively, we can go up from the substrate
by stacking multiple layers of capacitor electrodes to increase the "stacked" capacitor
area (FIG. 35b). Other tricks that have been tried are to purposely create
a rough polysilicon surface on the capacitor plates to increase the surface
area. In the future, alternative materials may be used. For example, the
ferroelectrics have much higher dielectric constant than SiO2 and offer
larger capacitance without increasing area or reducing thickness. Promising
materials include barium strontium titanate and zirconium oxide.
FIG. 35 Increasing cell capacitance by exploiting the vertical dimension:
(a) trench capacitors involve etching a trench in the substrate so that
the larger area on the sidewalls can be used to increase capacitance; (b)
stacked capacitors go "up" rather than "down" as in
trenches, and increase capacitor area by using multiple polysilicon capacitor
plates or "fins," as well as by exploiting the topography of the
cell surface.
FIG. 36 Flash memory cell structure: (a) cell structure shown along
the channel length showing the control gate (wordline), floating gate below
it, the source and the drain (bitline); (b) view of cell along the width
of the MOSFET. The various coupling capacitors to the floating gate are
shown.
Flash Memories. Another interesting MOS device is the
flash memory, which is the most important type of nonvolatile memory. The
memory cell structure is shown in FIG. 36. It is very simple and compact,
and looks just like a MOSFET, except that it has two gate electrodes, one
on top of the other. The top electrode is the one that we have direct electrical
access to, and is known as the control gate. Below that we have a socalled "floating" gate
that is capacitively coupled to the control gate and the underlying silicon.
The capacitive coupling of the floating gate to the various terminals is
illustrated in FIG. 36 in terms of the various coupling capacitance components.
The floating gate and the control gate are separated by a stacked oxidenitrideoxide
dielectric in typical flash devices. The capacitance between these two gates
is called CONO because of the oxidenitrideoxide makeup of the dielectric
stack. The total capacitance CTOT is the sum of all the parallel components
shown in FIG. 36.
CTOT = CONO + CTOX + CFLD + CSRC + CDRN (eqn. 15)
where CTOX is the floating gatetochannel capacitance through the tunnel
oxide, CFLD is the floating gatetosubstrate capacitance in the LOCOS field
oxide region, and CSRC and CDRN are the gatetosource/drain overlap capacitances.
Since it is isolated by the surrounding dielectrics, the charge on the
floating gate QFG is not changed by (moderate) changes of the terminal biases.
QFG = 0 = CONO(VFG VG) + CSRC(VFG VS) + CDRN(VFG VD) (eqn. 16)
We assume that the substrate bias is fixed, and hence ignore the contributions
from CTOX and CFLD, which couple the floating gate to the substrate. The
floating gate voltage can be indirectly determined by the various terminal
voltages, in terms of the gate, drain, and source coupling ratios as defined
in Eq. (eqn. 17).
VFG = VG ~ GCR + VS ~ SCR + VD ~ DCR (eqn. 17)
where
GCR =
CONO CTOT
DCR =
CDRN CTOT
SCR =
CSRC CTOT
The basic cell operation involves putting charge on the floating gate or
removing it, in order to program the MOSFET to have two different VT/ s,
corresponding to two logic levels. We can think of the stored charge on
the floating gate to be like the fixed oxide charge in the VT expression.
If many electrons are stored in the floating gate, the VT of an NMOSFET
is high; the cell is considered to have been "programmed" to
exhibit the logic state "0". On the contrary, if electrons have
been removed from the floating gate, the cell is considered to have been "erased" into
a low VT state or logic "1".
How do we go about transferring charges into and out of the floating gate?
To program the cell, we can use channel hot carrier effects that we discussed.
We apply a high field to both the drain (bitline) and floating gate (wordline)
such that the MOSFET is in saturation. It was discussed that the high longitudinal
electric field in the pinchoff region accelerates electrons toward the
drain and makes them energetic (hot). We maximize such hot carrier effects
near the drain pinchoff region in a flash device by making the drain junction
somewhat shallower than the source junction (FIG. 37a). This can be achieved
by a separate higher energy source implant that is masked in the drain region.
If the kinetic energy of electrons is high enough, a few can become hot
enough to be scattered into the floating gate. They must surmount the 3.
1eV energy barrier that exists between the conduction band of Si and that
of SiO2, or hot electrons can tunnel through the oxide (FIG. 37b). Once
they get into the floating gate, electrons become trapped in the 3. 1eV
potential well between the floating polysilicon gate and the oxides on either
side. This barrier is extremely high for a trapped (low kinetic energy)
electron. Therefore the trapped electrons essentially stay in the floating
gate forever, unless the cell is intentionally erased. That is why a flash
memory is nonvolatile.
FIG. 37 Hot carrier programming of the flash cell: (a) flash memory
cell structure with typical biases required for writing into the cell. The
channel of the MOSFET is pinched off in saturation; (b) band diagram along
a vertical line in the middle of MOSFET channel showing hot electrons in
the channel being injected across the gate oxide and getting trapped in
the floating gate.
FIG. 38
FowlerNordheim tunneling erasure: (a) flash memory cell structure with
typical biases required for erasing the cell; (b) band diagram as a function
of depth in the gate/source overlap region of the MOSFET showing quantum
mechanical tunneling of carriers from the floating gate into the oxide,
and subsequent drift to the source.
To erase the cell, we use FowlerNordheim tunneling between the floating
gate and the source in the overlap region (FIG. 38a). A high positive
voltage (say ~12 V) is applied to the source with the control gate grounded.
The polarity of the field is such that electrons tunnel from the floating
gate into the source region, through the oxide barrier.
The band diagram (along a vertical line in this overlap region) during
the operation is shown in FIG. 38b. Interestingly, in a flash device we
make use of two effects that are considered to be "problems" in
regular MOS devices: hot carrier effects and FowlerNordheim tunneling.
FIG. 39 Drain (bitline) current versus control gate (wordline) voltage
transfer characteristics of the MOSFET in a flash cell: if the cell is programmed
to a high VT (logic "0"), and a read voltage is applied to the
wordline that is below this VT , the MOSFET does not conduct, and there
is negligible bitline current. On the other hand, if the cell had been erased
to a low VT state (logic "1") the MOSFET is turned ON, and there
is significant bitline current.
During the read operation, we apply a moderate voltage (~1 V) to the bitline
(drain of the MOSFET), and a wordline (control gate) voltage VCG that causes
the capacitively coupled floating gate voltage to be between that of the
high VT and the low VT state of the programmed flash memory cell (FIG. 39).
There will be negligible drain current flow in the bit line (drain) for
the high VT case because the gate voltage is less than the threshold voltage.
We will then interpret the selected cell as being in state "0".
For the low VT case, since the applied gate voltage is higher than the threshold
voltage of the cell, there will be drain current flow in the bitline (drain),
and this can be interpreted as state "1". The read operation can
be understood by looking at the transfer characteristics of the MOSFET in
the programmed and erased states (FIG. 39).
