Guide to Computer Architecture and System Design--MEMORY ORGANIZATION

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The stored program concept is on the Zenith assuming a widely varying parameters like memory speeds, store reliability, computational complexity, well standardized application bases and cost-effectiveness.

Whereas the technology helps to meet the speed and reliability aspects, the domain of intelligent algorithms for system storage management and user algorithms towards program maintenance in the perspectives of software engineering will certainly reflect the ways of improving memory efficiency on a generalized sense. It is often said that memory cost is the machine cost; thus the memory size the system supports is a major criterion besides the slowly refined virtual memory management towards good I/O management policies in real-time.

Under the general context the memory is distributed all over a computer installation, whereas the dedicated end-usage confined to low compute needs and flexible process control areas dictate much on a hardware biased design with memory locatable microcontrollers in the Application specific Integrated Circuits group (ASICs).

Let US begin giving credit to the electronics technology since its inception in 1940's and then categorically discuss on the storage capabilities.


Electronics is the study of the behavior of charged particles called electrons at differing environments. Let us start stating a few terms in nuclear physics.

An electron is an elementary particle having a rest mass of 9.1091 x 10 31 kg, 1/1836 that of a hydrogen atom, and bearing a negative electric charge of 1.6021 x 10 19 coulombs

(4.80298 x 10^-10 ESU).

Electrostatic unit, ESU of charge called statcoulomb is that quantity of electricity which will repel an equal quantity, 1 em distant from it in vacuum, with a force of 1 dyne.

Radius of electron is 2.81777 x 10^-15 meters. A hole may be regarded as a mobile vacancy with a positive electronic charge and a positive mass; it is thus mathematically equivalent to a positron.

A free electron is one which has been detached from its atomic orbit.

Electron· volt, eV is the unit of energy used in nuclear physics. The increase in energy or the work done on an electron when passing through a potential rise of 1 volt.

1 eV 1.6021 x 10^-19 joules

1 MeV

1 GeV

106 eV;

109 eY.

Valency is the combining power of an atom of an element, the number of hydrogen atoms which an atom will combine with or replace; for example, the valency of oxygen in water, HP, is 2.

Semiconductor is an electrical conductor whose resistance decreases with rising temperature and presence of impurities, in contrast to normal metallic conductors for which the reverse is true. The main semiconductors include Germanium, silicon, Selenium and Lead - Telluride. Pure or intrinsic semiconductors have negligible conductivity and the conduction has little flexibility; the process of adding impurity atoms of adjacent valency groups is called Dopine and the extrinsic semiconductors so obtained become valuable.

Germanium and Silicon are tetravalent. When pentavalent impurity atoms such as phosphorous, antimony, arsenic or bismuth are used in doping will result in n-type semiconductor. The trivalent impurities include boron, gallium, indium and aluminum.

As temperature of a semiconductor increases the mobilities u_n and u_p decrease, but the decrease in mobility is more than offset by the increase in the carrier densities n and p and the resistivity decreases with increase in temperature. Thus, the semiconductors are also used in temperature measuring devices.

The compounds of Germanium are rare. It is a brittle white metal and used in transistors. Silicon is a nonmetal similar to carbon in its chemical properties. This occurs in two allotropic forms, viz., a brown amorphous powder and dark grey crystals.

This is used in alloys and in the form of silicates in glass. Silicones are also widely used.

Some of the properties of basic semiconductor materials.

Germanium Silicon

Valency 4 4

Atomic number 32 14

Atomic weight 72.59 28.086

Specific gravity 5.35 2.42

Melting point 937.4°C 14200C

A p-n semiconductor junction is formed when there is a change along the length of a crystal from one type of impurity to the other. At a p - n junction, an internal electric field is created between the charged impurity ions of the two types. This field is sufficient to prevent the drift of electrons from the n side to the p side of the junction, and the drift of holes in the opposite direction.

The cut-in voltage E of p - n diode for Germanium is 0.1 to 0.2 volt whereas for silicon it is 0.6 to 0.7 volt. The larger delay in switching characteristics of silicon accounts for germanium being used in faster digital circuits. For reasons of more power dissipation capabilities and ease of fabrication, invariably silicon is used in memory constructions.

N - type devices are faster because electrons mobility is greater than hole mobility.


Table 1 Compares the operational features of the versatile transistor technology.

[Conventional Junction Transistor

-Bipolar Input is forward biased so low Rin Current operated device Finite offset voltage Used in CPU storage memory capacity ]

[Field-effect transistor

- Unipolar High Rin Voltage controlled No offset voltage.

High fanout, capacity and higher Less packing density. ]


Certain typical parameters for standard IC families are charted in Table 2.


Table 2 Typical parameters for standard I C families


EeL non saturated logic finds applications in high speed computers while C M 0 S is preferred in microprocessors since its inception in 1970's.

Georg OHM (1787 - 1854) is responsible for all electrical measurements thanks to the Ohm's Law.

"The ratio of the potential difference between the ends of a conductor and the current flowing in the conductor is constant", given by Ell a R ohms.

Subsequently, Gustav Robert KirchhoffC1824 - 1887) established his well proved electrical theorems, namely, Kirchhoff's voltage law. "The sum of the voltages around a closed loop is Zero."

Kirchhoff's current law:

"The sum of the currents entering a node equals the sum of currents leaving that node".

The above axioms find a great deal of efforts in designing integrated circuits in V L S I area. Reduced cost and size, improved reliability and speed of operation, and increased packing density are among the technological advancements catering to the modern memory-based digital systems.


Besides the precious and limited processor memory also called registers, the adjacent working memories during a process are termed primary memories. The abilities of C P U registers include storage, counting and shift operations. They are constructed of very high speed logic to meet processor - memory bandwidths on computing platforms. The registers are more often labeled for dedicated activities while a few may incorporate the flexibility for programmability on well designed programmed machines.

Since more CPU in storage demands for larger space on the Integrated chip and high number of connectivity shells with more on-process book- keeping, the arithmetic logic units may become underutilized in processor management, a key function for any operating system. In this context, the variety of semiconductor memories and advantageous fast access stores like cache memories for real immediate process needs have come to stay on single stand-alone systems of larger wordlengths. In early systems, the ferrite core served as main store as in the T DC - 312, a 12 bit machine which confined a byte to be made of six bits. The main merit of these batch processing single job machines was the non-volatility offered by core memories for a safe storage under power failures. But the standard byte refers to a set of 8 bits in present day memory organizations. The cores are the only magnetic memories employed earlier as main stores.

The 1 bit storage unit consist of a small toroidal (ring - shaped )piece of magnetic material (ceramic). Minimum dimension for typical ferrite cores are 0.5 mm outside diameter with a central hole of 0.4 mm and thickness of 0.15 mm. Switching speed increases with reduction in core size.

Fig. 1. depicts the core with the square-loop characteristics. A substantial current 1m of the order of several mA is required to cause switching. The mc -312 used main memory of size 4 K words where 1 word = 12 bits. The maximum memory size is known to be 128 K of word lengths reaching up to 32 bits or more with core storage.

Fig. 1 Square loop characteristics

The core memory organization can be categorized as follows:- Linear select and coincident current memory. This is word organized two-dimensional store. Fig. 2. shows the 2-D organization.

Fig. 2 Linear 2D select organization

The sensing or reading memory is of destructive type and more generally the word has to be rewritten after every read operation. Similarly the write operation on selected cores is followed by the verification of the data register contents for faithful systems.

Three wires are used across each core thus making 2D memories faster. But it requires 2n word drive amplifiers and m bit drivers (sense amplifiers). Coincident current memory Three-D organization: This is also called bit organized space. The store is arranged as a set of planes equal to m (word size of machine).

This uses m Sense wires and m inhibit drivers embedding each core. The core-size becomes large and reduces the achievable speed in memory transactions.

For N, the number of memory locations assumed to be exactly perfect square, this method needs 2√N drivers for rows and columns preserved to be a square matrix.

For illustration, a 64 x 8 word organization in 2D becomes 8 x 8 x 8 bit organised in 3D, thus reducing the associated drive circuitry very much for large values of N. 2 1/2 D memory technique :-

This is employed for fast operation with large size memory. One core plane is used for each bit of the word and coincident current technique is employed as in 3 D. But each plane requires separate x drivers. The core arrays need not be square. The y column drivers are shared by all the core planes. M sense wires are used, one per core array.

Thus, this meets the dual effects of 2 D and 3 D with homogeneous construction. The maximum access time is product of clock period and loop bit size.

Example: A system with frequency of 20 MHZ has a memory density of 8 K.

What is ATmax?

AT max = 1/20 x 10^6 x 8192 = 409.6 uS.

It there are 8 planes, then

AT max =409/. 8 = 51.2 uS

Corresponding to the 2 1/2 D technique.

Further trends for magnetic core as main stores take different forms like list below: Thin film memory; superconductive or cryogenic memory, plated - wire type and magnetic bubbles.

Magnetic film memories have very thin flat layer of nickel iron alloy as the memory element. Along one geometrical axis magnetization is easy. They can be arranged in 2 D form.

Cryogenic memory has large packing density of the order of 15,000 cells per square inch and also fast switching speed. Some metals have very low resistance (0 ohm) at very low temperatures. The switching from super conductive to conductive state is used to designate the 1 and 0 binary values. Coincident current selection is provided for organizing data on this. But it requires a very low temperature container (near 4°K). Plated wires are similar to thin film memory. Magnetization is easy along the wire circumference and hard along the axis. 2-D scheme is preferred.

Magnetic bubbles are static devices which has the property that data can be recorded by the polarity of small zones and the zones get shifted along a path by applied field (shift register). It offers high density, reliability at low cost.

With the advent of microprocessors in 1970 the semiconductors have taken over the main memory functions. It holds the current program in execution besides accommodating the operating system, compilers/Assemblers which occupy a significant fraction of the total random access store with a high activity ratio. The semiconductor or electronic memories are all considered to he of nondestructive nature, random access type and volatile but for the ROM (read only memory) category" A memory is said to be volatile when its contents are lost with power loss. The access time considered to be one of the primary parameters for a good system throughput and turn around time is fastest for main memories and is random meaning the time required to access any portion or part of the store is identical. The foremost factor considered is the clock of a CPU on a synchronous system where all the activities of processing is governed by the system clock. Thus, today C P Us with clocks ranging from 1 MHZ to 60 MHZ is not uncommon. Crystal docks are preferred and employed for they are very accurate and precise to establish a total control over the operating system. The improvement in clock speed also implies a good feed rate possible to the arithmetic logic units.

A computer system is considered to be strictly a sequential machine involving both synchronous and asynchronous activities which calls for electronic docks in binary systems.

In this sense, a clock is an astable multivibrator (relaxation Oscillator) implemented using electronic devices and circuits. In general, power dissipation of a logic circuit is defined as the supply power required for the gate to operate with a 50% duty cycle at a specific frequency (varies from few uW to 50mw/gate). Fig. the circuit for an astable multivibrator.

Fig. 3 Circuit of astable multivibrator

The ON and OFF times can be made equal by using R B1 = R B2 = RH ; and C1 = C2 == C, the time period of the square wave is T == 1.4 RB.C. Moreover, the circuit operates with Q1 and Q2 switching in opposite states thus providing also the inverted clock for use in master-slave flip flops devised to provide buffering and avoid racing in sequential machines.

A monostable multivibrator or a one-shot is stable in one of the states but unstable in the other state. The IC 555 is one which can be employed both as an astable or monostable multivibrator with varying duty cycles over a wide range of frequencies. Usually the square wave is differentiated by a simple RC network to generate triggering pulse (as clocks) to operate various types of flipflops in synchronous machines. For CPU activities, synchronous design is simple at the cost of the idle time of processing element.,. In the domain of parallel processing for pipelining activities on a single sequential machine., the asynchronous operation can be well achieved with careful design for idling CPU. This sort of a pipelined approach also calls for cache memory used as slave-store in the powerful I/O activities concerned of the central processing elements.

A bistable multivibrator is stable in both the '1' and '0' states which becomes an elementary cell in a primary semiconductor memory. The circuit behavior strictly follows the Newton's first law of thermodynamics, namely, "every body tend., to remain in its state until and unless an external force attempts to change the state under supervision". Thus the bistable circuit is more often known by the term ''flipflop'' which are usually clocked for their applications. Before delving into memory organizations, the various types of flip flops are explained to advantage.

A bit is a binary digit which can be either 0 or 1. A byte is considered to be a set of 8 bits while a nibble is made up of 4 bits. Fig. 4. shows the circuit for a clocked RS flipflop.

Fig. 4 Circuit of a clocked RS flipflop

The flipflop provides its status both in true and complemented form Q and Q, the excitation S = R = 1 is never possible by the definition of a bistable multi vibrator.

Moreover, observe the change in the next state Qn + 1 only with the application of a clock pulse. Fig. SCa) shows the block of a D flipflop which is a derived one from the S R flipflop.

Fig. 5(a) 0 flipflop (b) Buffer tristate logic

Fig. 6 JK flipflop with excitation table

Here Q = D is the characteristic equation and just the R input is inverted and fed to the S input of a S R flipflop. This is known as voltage follower and used in buffering.

With tristate logic as shown in Fig 5 (b), this D-type latch acts as a temporary storage for more of the interrupt driven information. These latches are much valuable in microprocessor based systems for the interacting I/O actions.

The more versatile JK flipflop allows the forbidden combination of S = R = 1 of a S R flipflop making JK meaningful for register storage within a microprocessor. Fig. 6 shows the block symbol of JK flipflop with the excitation table.

More often, the flipflops are provided with clearing options and preset to any desired state as shown. The master/slave concept is often used for buffering and to avoid racing in sequential circuits. The JK flipflops are used in counters and shift registers for rotating displays. A register is supposed to consist of 'm' flipflops where m denotes the CPU word length.

The registers and counters with varying degrees of abilities are constructed by careful design using the sequential logic circuits to make the storage well organized. The T flipflop is one which accepts a clock of frequency, fin and provides an output waveform (square) with frequency four = fin/2, which can be employed for timing control in sequential systems. In general, n ''T'" flipflops in cascade will provide an output frequency f_out = f_in /2n.

Thus the various types of flipflops provide a sitting status for the main store elements and their dynamic usage in complex architectures. In addition, the PSW (program status word) dictates and reflects the status of the current user program being executed on the machine by means of powerful Flags. Only certain flags can be preset at user's will like the carry flag of the 8085 microprocessor. The other flags include Zero, Auxiliary carry, parity and sign. 8086 has nine flags in total. Also the processor status is indicated by the process effects or defects more on a batch system by indicating if the machine is in Fetch, Execute, Halt or other states for the system operator to interact on a regular basis as of a supervising robot. No doubt, the computer is a faithful worker as long as the system behaves well like meeting the Asimov's law of robotics. Hence, modem computer systems must incorporate detecting tampering of machines by any means (example software viruses, etc) and make alarms and shut down the process for preventive maintenance to qualify to be a secure system done to safety. The sequential state minimization is further conveyed in section 1. and fault - tolerance addressed in section 5. Fig. 7 shows the J.K. flipflops used as mod - 8 ripple counter.

Fig. 7 JK flipflops used as mod-8 ripple counter.

Just using the complemented output Q to clocks will imply a down counter. Any counter to m states, mod - m counter, needs n flipflops for realization, where, (2n • 1 < m < 2n).

Most of the registers and counters are also available as M S I chips. Multiplexers and De-multiplexers again playa vital role in addressing the total STORES of a computer system when access can be fruitfully achieved.

A decoder takes a bit pattern as input and selects only one of several output address lines at any point of time serving as a hardware unit during semiconductor memory access. Instruction cycle decoding and machine cycles encoding is a regular procedure at runtimes to present useful expected outputs of a computer which otherwise is impossible in real-time. The amazing real-time areas where computers have carried a name include online Reservation systems, data base management for information retrieval, computations for space exploration and image transmissions in global communications and computer network.,.

A random access memory ( RAM ) is a Read/Write memory which forms the major portion of the addressable memory space. It is volatile; the read out is nondestructive.

All electronic memories follow the random access method. Presently these are byte organised and only the instruction takes care of the number of bytes accessed on every instruction. Fig. 8. gives the byte organized nature of electronic memories.

Fig. 8 Electronic memories.

The memory chip must have provision for read/write control, data input lines, sense data output'), and address input pins to access anyone location of the chip capacity at any point of time as shown.

A 12 to 2^12 line decoder is far expensive than a 6 to 26 line decoder. This calls for differing 3-D, 2^1/2 D organizations as well as increasing the component counts and reducing and with each location storing 16 bits is called a "16-bit 4096-word" memory, or in the vocabulary of computer trade a "4K 16-bit"memory. 8085 CPU can address to a maximum of 64 K bytes of memory, whereas 8086 with 20-bit address bus accommodates 1 mega bytes of memory. 8086 also uses segment registers and partitions the memory user space into 4 x 64 K bytes partitions for parallel data bus. AD7 - ADD meeting both needs. At times, some of the memory addresses are used for secondary and end terminals (I/O units) which is called memory-mapped I/O. This concept may also be useful in process instrumentation area. The 8085 CPU uses I/O mapped I/O with 10/M pin indicating the address redirection. But today with reliable and fast switching areas of communications, Bit slice processors and hit organization of memory become irresistible for error control.

The bipolar RAM has less access time of the order of 10 ns but it needs large area and has high power dissipation.

The MOS RAM has access time of the order of 1 uS but needs less area and has low power dissipation. Fast memories are used in cache stores whereas the MOS technology fits the usual program store. Gold doping to reduce transistor recovery time as well as Schottky diode clamping to prevent transistor saturation are used with TTL configurations to increase speed. ECL is a non saturated logic offering very high speed at a higher cost/bit. Table 3 depicts the factors associated with various memory technologies.

Table 3 Memory performance data.

Fig. 9 shows a static MOSRAM cell.

Fig. 9 Static MOS RAM cell

Q1 and Q2 form the flipflop which is the basis of the storage cell. Q3 and Q4 sense as pull up resistors for transistors Q1 and Q2.

If coincident memory current selection is used, a part of the address is decoded to choose a particular row (x address). The X address line controls Q5 and Q6 of all cells in the appropriate row. The remainder of the address is decoded to determine the particular column (Y address) that is to be read. The output from decoder is applied to the y address line and controls Q7 and Q8 of the appropriate column of cells. If Qs through Qs are turned ON, a current will flow in one and only one of the two bit lines (X, Y select). A sense amplifier is provided to convert the current signal into a voltage level. The state of the flipflop (Q1 and Q) is not altered by the REA 0 operation. In order to perform the W R I T E operation, the proper cell must be addressed (Qs through Q8 turned ON ) and the appropriate voltage levels must be applied to the bit lines by the W RITE amplifiers. This sets the desired state of the flipflop. Static MOS memories consume less power and have high packing densities.

Dynamic MOS memory cell is shown in Fig. 10

Fig. 10 Dynamic MOS memory cell

In dynamic memories restricted to M O S technology, storage takes place as charge on gate substrate capacitance. Refresh is required once every few ms, and consumes lesser power. This also offers high speed relative to static cells. Extra timing and logic circuitry is needed for refresh cycles. To write into the cell requires holding the write bus at a low logic level; then a low level at the write data input charges the gate capacitance; stores a 1 in the cell. With the write bus held low, and a high logic (Vee) at the write data input discharges the gate capacitance. To read from the cell requires holding the read bus input at a low logic level; if the gate capacitance is charged, the read data line goes to + Vss. It offers store capacity of about 16,000 cells/IC.

The next type of powerful semiconductor memory is ROM (read only) which i:; utilized for storing monitor programs, Table look up entries, File management data of disk stores, sub routines, dedicated software for microprocessor based instrumentation systems and so on. The ROM is essentially nonvolatile and frequently restricted to MOS technology. Microprogrammed ROM's, at times meet the complex arithmetic operations in RISC architectures meaning more in storage of CPU being utilized successfully. Fig. 11 shows the block for a 1K byte ROM.

Fig. 11 Block diagram of 1KB ROM

At times also diode ROMs are employed in routine advertisements and displays. A more flexible approach is allowing people to program the ROM which insists on PROM that makes use of fusible links which can be broken when a high current is passed through it. Initially every bit is set to 1.

An EPROM (Erasable programmable ROM) is a chip, wherein the fusible links can be re-generated with exposure to ultraviolet light so that it can be reprogrammed. But even to change a few cells, the whole chip must be erased.

EAROM s (electrically alterable) give the advantage of making even a few changes due to mistakes done earlier while programming. These are the various types of read only store which improves the user volume by leaps and bound" to the electronic stores.

Cache Memory

The speed offered by these chips (cache memory) are compatible with the processor elements. It just takes few10's of ns for accessing the cache area. The size of cache is low compared to the primary RAM area and this often serves as a copy (image) of the main store as well an output buffer in meeting the memory and processor bandwidths. The timing differences is governed by the adequate equation tp < tm < td, where tp is the time spent on processing units, tm is primary memory access time and td is the devices interrupting times. With this variable ratio of tp : tm : t d , today there exists multiuser terminals on a single CPU machine like the UNIX environment, more often catering to uni-programming (one language) environment at any particular point of time. Also on batch processing machines, the CACHEs plays crucial role of voluminous data processing in meeting the desired throughputs of machines.

The major applications of caches include, storing the current portions of program in use on a selective mode with a sensitive approach; accommodating the executable subprograms; storing input data like arrays and data files; in search applications the relevant files with good virtual memory management and also CPU output buffering activities.

Every time an address is given out of the CPU, the availability is first checked in the Cache area; if available it implies a Cache Hit. Otherwise it goes usually with the main store seeking for the data. Today systems have been well designed to achieve cache hit ratios of more than 90%.

Cache Hit ratio = Total no. of cache hits / Total no. of memory references

This portion is also employed as content addressable memory ( CAM). Here, only certain bits are selectively mapped for faster decisions. In CAM, read operation follows a MATCH operation. Thus, matched words are obtained as read output. Complex operations like less than, greater than, next lower, next higher are also performed with CAMs. The PERFORM and SEARCH ALL verbs of COBOL remind this feature. SORT and MERGE utilities on data files again implies the cache area fitting to both program and data files.

This is also referred in the literature as content addressable memory. The function of the operating systems become much more effective on process management with the inclusion of cache memories. It has become compulsory of every interactive on-line machine (including a PC) to include the powerful cache storage. We can comment only saying that cache is a cash transaction while the usual RAMs are check driven in terms of access speeds.

Similarly, a microprogrammed control unit utilizes a ROM to store binary control information. Mask programmable ROMs are also used for combinational logic circuits realizations. ASCII to EBCDIC code converters use ROMs for portability across machines and compatibility for printing data outputs. The visual display using CRTs more often accommodate up to 4k-bytes of semiconductor memory with EBAMs technology to cater to the ever interactive DMA environment on interrupted machines. The front end processor acting as a channel gathers input from terminals and routing results back to users will relieve the main CPU in order to concentrate on the real computing tasks ahead of it. Thus the main CPU has to deal with one interrupt, that of the block transfers. By inclusion of the front end 0/0) processors and a good blend of electronic memories, the best performance output can be achieved in computer applications.

Programmable logic array

In the realm of combinational logic designs where the number of don't care conditions is excessive, it is more economical to use LSI chip PLA. A PLA is similar to ROM in concept; however, it does not provide full decoding of the variables and does not generate all the minterms as in the ROM. In the PLA, the decoder is replaced by a group of AND gates, each of which can be programmed to generate a product term of the input variables.

The AND and OR gates inside the PLA are initially fabricated with links among them. The specific boolean functions are implemented in SOP form by opening appropriate links and leaving the desired connections. Fig. 12 gives the PLA block diagram.

It consists of n inputs, m outputs, K product terms, and m sum terms. The product terms constitute a group of K AND gates and the sum terms constitute a group of m OR gates. Links are inserted between all n inputs and their complement values to each of the AND gates. Links are also provided between the outputs of the AND gates and the inputs of the OR gates. Another set of links in the output inverters allows the output function to be generated either in the AND-OR form or in the AND - OR - INVERT form.

Fig. 12 PLA Block Diagram

The size of the PLA is specified by the number of inputs, the number of product terms and the number of outputs (the number of sum terms is = the number of outputs). A typical PLA has 16 inputs, 48 product terms and 8 outputs (TTL IC type 82S100). The number of programmed links is ((2n x K) + (k x m) + m) whereas that of a ROM is (2n x m). With the chip mentioned, (32 • 48) + (48 • 8) + 8 = 1928 links.

Field PLA can be programmed by the user by means of certain recommended procedures. PALs are referred to as programmable gate arrays. A Typical PAL may have 10 inputs, 8 output') and two product terms per output. A PAL differs from a PLA that the number of terms per output is fixed, imposing more constraints on the designer.

Some PALs are available with feedback and others with registered output and feedback.

A PAL having 8 inputs and 8 outputs of which 6 are registered, with all outputs feedback uses two 1 of 8 multiplexers and five NOR gates.

In arithmetic for data representation, use of the E format not only accommodates a wide range of values but also simplifies the computational requirement by effective storage utilization and optimization of machine resources. The algorithm area for arithmetic again give a big profit on compute base environments. In numerical methods involving lot of iterations which has to converge either based on error set limits or on time bound criterion, the cache memories are a boon to application engineers. Thus computer science is a domain that can be augmented and assisted in many a problem by giant mathematicians. Thus machines in future will really meet the concept of number crunching activities. Fig. 13 shows memory arrangement of a computing system.

The cost of a machine is very much dependent on the main memory size it supports.

Starting with 4 K of RAM, today computers can support mega to gigabytes of this valuable storage besides catering to bulk amount of secondary or auxiliary data-points. With disk operating systems, the hard disks have begun to occupy a more or less prominent place in real computers that can accept a variety of Languages.

Fig. 13 Memory arrangement of a computing system.

3. Secondary and Auxiliary Storage

With the cyclic access store, large amount') of storage are involved and many a time are retrieved in blocks containing many words. Digital magnetic memories are confined to store medium like magnetic cassette and cartridge tapes, Magnetic Drum and Diskettes.

The main parameter distinguishing them is the type of access, either serial or sequential.

With these storing elements, a very large volume of data can be stored indefinitely due to the non-volatile nature of this auxiliary media. The system programs, compilers, packages, various editors, diagnostic and debugging tools including the operating systems reside on these disk and tape mountings on large installations, besides the ever growing me space for the user community. Thus rightly, this place could be considered me memory place for the fuel as well as food for the turn-around-time of any job. Turn-around-time is the of a source file to the generation of the desired output results. Even the spooling is an activity which requires this mass medium for a batch printout at a later time on multiuser platforms.

Magnetic Tape Memory

These are used as external storage devices and as high speed I/O system. They provide serial access. The total body of information passes a reading device in serial fashion, and the average retrieval time is half the total time necessary for a complete pass of data recordings. The home entertainment units require high fidelity amplifier and Supersonic bias used to achieve linearity, with multimedia trends. The computer tapes store data as I and 0 using return to zero (RZ) and NRZ (non return to Zero) techniques. It stores individual alphanumeric characters across the tape in 8-bit ASCII code, one track to establish uniform parity in reliable systems. The batch IBM machines use the standard 8 bit EBCDIC (pronounced as eb-si-dik) code for data processing. The computer tapes are generally wider and longer than tapes of entertainment units typically 2400 to 3600 feet long and 1/2 to 1" in width. Plastic tapes coated with metal oxide on one side is used for durability. 20 million bits of information can be stored on a simple magnetic tape unit.

Data is read/written simultaneously on all tracks but recorded serially in each track.

Tape speed is about 100 inches/ second with a capacity of 1200 characters/inch. Fig. 14 shows the tape drive mechanism. RIW heads can be single gap or dual gap heads. Te information from store registers is written on the tape surface by write head after amplification. The tape moves and the recorded information comes below the Read-head. Thus, the information so recorded is immediately read out, amplified and then applied to a register known as Readout register. The contents of ROR and computer O/ P register are compared with comparator circuits. If different, an alarm signal is given and tape drive stops, otherwise recording continues.

Fig. 14 Tape record.

The address of the record is first read in a read our register (ROR) through the read head and amplifier. The desired address in address register is compared with ROR. If same, a signal is sent out to the AND gate which enables the AND gate to store the record in computer primary memory. Similarly the output from computer can be written to the tapes by write amplifiers while recording. The tape drive incorporates the start, stop, locate tape functions.

Fig. 15( a) Circuit for locating magnetic tape records

Fig. 15 (b) Record formatting

The record length is variable determined by word size of computer. There is a uniform inter record gap (IRG). Records are grouped together into files, files separated by file gaps, as in Fig. 15(b). Blanks are provided on tape to indicate the start and end of file. This medium being of serial access type, is a slow device. Also these involve a considerable amount of electromechanical engineering, are somewhat inflexible and regarded as less attractive than discs. Nevertheless, they serve as an essential medium for distributed data storage and off-line information for real records.

Magnetic Drum memory

These were among the first devices to provide a relatively inexpensive means of storing information and have reasonably short access times. Fig. 16(a) shows a magnetic drum.

It consists basically of a rotating cylinder coated with a thin layer of magnetic material which possess a hysteresis loop similar to that of material used in magnetic cores.

Fig. 16(a) Magnetic drum

A number of recording heads are mounted along the surface of the drum. These are used to read and write information from the surface of the drum by sensing or magnetizing small areas as shown. As the drum rotates, a small area continually passes under each of the heads. This area is known as a track. Each track is divided into number of cells each of which can store 1 bit. Generally, one of the tracks is used to provide the timing for the drum. The drum is addressed by a track number and sector number in its address field as in Fig. 16(b).

Fig. 16(b) Track number and sector number

The size of the metallic drum is typically 12" in diameter and 8" in length. The outer surface is divided into number of tracks or channels. 20 tracks per inch is a common measure. Some drums have multiple R/W heads per track for parallel data transfer. The drum is rotated at a constant speed of 1200 to 15000 rpm, average speed being 3600 rpm.

The binary data in the form of magnetization can be stored in the tracks at various locations. Each track can store a large number of bits, 200bits/track inch of the circumference of a drum is a typical figure. Thus more than 10^6 bits can be placed on a 12" dia, 8" long drum. This capacity is obtained at a low cost. The selection circuit for the R/W head is simpler because ·of ease of drum addressing. Considering a rotational speed of 10,000 rpm, Time for 1 revolution = 1 / 10,000 --x 60 sec= 6 msec. The average A access time = 3 m sec.

Usually larger drums have slower speed of rotation while small drums have large speeds of rotation.

Example: A certain magnetic drum is 12 inches long and 12" in diameter. It has in total 200 tracks, with a recording density of 500 bits/inch. Calculate the drum capacity in bytes. If the speed of rotation is 3000 rpm, calculate the average access time.

The bits / track = 22 / 7 x 12 x 500 = 18, 840 bits.


The drum capacity in bytes = 18, 840 x -8- = 4,71,000 bytes

A speed of 3000 rpm = 50 revolutions per second.

1 Time for 1 rotation = 50 sec. = 20 ms.

The average access time = 1/2 (20) = 10 ms.

Drum memory can be organized in bit serial form where all the bits of a word are in' the same track; in parallel organization, tracks put together represent a word and it has a fast data rate only at the expense of more R/W heads working simultaneously. When dealing with BCD arithmetic data and eb-si-dik codes a combination of serial and parallel data representation has to be followed.

Thus, this memory provides a high data rate though it takes fairly large access times.

The recording methods can be return to zero (RZ), wherein the magnetization is in two directions for 1 and 0 bits but the flux on the magnetic surface within a track always returns to the reference value between two adjacent bits of information. In NRZ technique, the direction of magnetization changes whenever a "1" bit value is stored and this offers higher packing density. One track is used as origin or for indexing purpose for indexed sequential files in database managements.

Magnetic Disc Memory

Disc stores are used as VO for large computer systems. This has the features of cyclic access and non-volatility. The major classifications of disks are Hard and floppy diskettes.

The Personal computers use hard disks which is a fixed store unit. The RSX - 11M of DEC computers are based on Hard disk units. The Unix also utilizes the disk storage for the many terminals it supports. Exchangeable Hard disk units provide the facility for removal and replacement of the disks when a very large volume of data is thought of.

With all disc systems a coating of magnetic material (ferrite) is applied to the surface of the disc platter. Writing and reading of data is performed by a recording/playback head positioned above the disc. The head is moved radially to select one of a number of concentric racks. Each head comprises a high-permeability split-ring core wound with a coil of fine wire. Fig. 17 shows the disc pack.

Fig. 17 Disk pack

The unit may also have a number of discs arranged vertically on a spindle. The time taken for interchanging disk packs is about 1 minute with batch systems. Both sides of the disc are used for storing data. Memory cycle time is the total time to read from the memory together with the restoration time in the case of destructive readouts. Data is stored on tracks. Each surface contains about 250 tracks. Disc diameter varies between 1 to 3 feet and are rotated at a speed of about 1800 rpm. The average access time is about 50 ms to 250 ms. The outer most track serves as the index track and a timing track gives dock pulses for synchronization purpose. NRZ type of recording is preferable.

Development of non-contacting heads with magnetic surface will improve the speed as well the life of disks. Formatting a disc is usual procedure to start using the memory which has a geographical layout of the medium as well the allocation space for various files of data and programs.

Floppy Disc Memory

Today every computer user has to take the floppy packs for his own workspace and data files concerning his own records. Thus this is a removable disc system similar to magnetic tape.

Capacities range from 256 k bytes to 1 Mbytes data. This is made of plastic material, 8" in diameter and is coated with ferrite of about 0.003" in thickness. It is always kept inside a plastic cover thus increasing the mechanical stability. Cleaning and lubrication is done with the cover. There is a hole at the centre through which the spindle of the drive unit rotate the disc. The 8" floppy has 73 data tracks. Each track has 26 sectors with 64 words/sector. The speed is 360 rpm. The average access time ranges from 200 ms to 500 ms. The tracks are commonly divided into sections called sectors, sector implying the minimum amount of data which can be transferred. Disks that are permanently attached to the unit assembly are called hard disks. A disk drive with removable disks is called a floppy disk more commonly used with personal computers. Now 5 1/4" and 3 1/2" miniature disks of high densities and fast access have come to stay. There is a notch provision for write protect facility on user sensitive diskettes. These play the dual role of portability and portability across machines. One has to be careful with the use of foreign disk memory units that they have to be inspected and checked thoroughly that they don't harm any part of the computer memories in terms of VIRUS. The slow I/O devices is discussed in the following topic on End input - output medium.



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Updated: Wednesday, March 8, 2017 18:47 PST